MSP430F4152IPM datasheet(16/82 Pages) TI

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MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

POST OFFICE BOX 655303

 DALLAS, TEXAS 75265

peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number

SLAU056.

oscillator and system clock

The clock system in the MSP430F41x2 is supported by the FLL+ module that includes support for a 32768-Hz

watch crystal oscillator, an internal very low-power low--frequency oscillator, an internal digitally-controlled

oscillator (DCO), and an 8-MHz high-frequency crystal oscillator (XT1). The FLL+ clock module is designed to

meet the requirements of both low system cost and low power consumption. The FLL+ features a digital

frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency

to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock

source and stabilizes in less than 6 s. The FLL+ module provides the following clock signals:

Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or a very

low-power LF oscillator

Main clock (MCLK), the system clock used by the CPU

Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules

ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8

brownout, supply voltage supervisor

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on

and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user

selectable level and supports both supply voltage supervision (the device is automatically reset) and supply

voltage monitoring (SVM, the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not

have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC

reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).

digital I/O

There are seven 8-bit I/O ports implemented—ports P1 through P7. Port P7 is a 7-bit I/O port.

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt conditions is possible.

Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.

Read/write access to port-control registers is supported by all instructions.

MSP430F4152IPM Datasheet(PDF) 16 Page - Texas Instruments