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ICS1532 Datasheet(PDF) 22 Page - Integrated Device Technology |
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ICS1532 Datasheet(HTML) 22 Page - Integrated Device Technology |
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22 / 36 page ![]() 110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR ICS1532 MDS 1532 G 22 Revision 060804 www.idt.com 10.2 Programming Flow for Modifying PLL and DPA Settings Figure 10-2. ICS1532 Flow for Capture/Input Clock PLL Start Scaler Determ ines m ode Changing PLL Param eters? Set Input, PFD G ain, Post Scaler and Feedback Divider Regs 0~3 YES PLL S/W Reset RegA=50h PLL Locked? Adjust PFD G ain and/or Post Scaler NO Set DPA Resolution, Reg5 and DPA O ffset, Reg4 YES DPA S/W Reset RegA=0Ah Correct Phase Relationship? NO Adjust DPA offset Reg4 Done YES NO |
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