HT45F43 datasheet(119/152 Pages) HOLTEK

119 / 152 page

The external interrupt pins are connected to an internal filter to reduce the possibility of unwanted

external interrupts due to adverse noise or spikes on the external interrupt input signal. As this internal

filter circuit will consume a limited amount of power, a configuration option is provided to switch off

the filter function, an option which may be beneficial in power sensitive applications, but in which the

integrity of the input signal is high. Care must be taken when using the filter on/off configuration

option as it will be applied not only to both the external interrupt pins but also to the Timer/Event

Counter external input pins. Individual external interrupt or Timer/Event Counter pins cannot be

selected to have a filter on/off function.

INTEDGE Register

Bit

76543210

Name

¾¾¾¾

INT1S1

INT1S0

INT0S1

INT0S0

R/W

¾¾¾¾

R/W

POR

¾¾¾¾

0000

Bit 7~4

unimplemented, read as

²0²

Bit 3~2

INT1S1, INT1S0: INT1 Edge select

00: disable

01: rising edge trigger

10: falling edge trigger

11: dual edge trigger

Bit 1, Bit 0

INT0S1, INT0S0: INT0 Edge select

00: disable

01: rising edge trigger

10: falling edge trigger

11: dual edge trigger

External Peripheral Interrupt

The External Peripheral Interrupt operates in a similar way to the external interrupt and is contained

within the Multi-function interrupt.

For an external peripheral interrupt to occur, the global interrupt enable bit, EMI, external peripheral

interrupt enable bit, EPI, and Multi-function interrupt enable bit, EMFI, must first be set. An actual

external peripheral interrupt will take place when the external interrupt request flag, PEF, is set, a

situation that will occur when a negative transition, appears on the PINT pin. The external peripheral

interrupt pin is pin-shared with the I/O pin PB5, and is configured as a peripheral interrupt pin via a

configuration option. When the interrupt is enabled, the stack is not full and a negative transition type

appears on the external peripheral interrupt pin, a subroutine call to the Multi-function interrupt vector

at location18H, will take place. When the external peripheral interrupt is serviced, the EMI bit will be

cleared to disable other interrupts, however only the MFF interrupt request flag will be reset. As the

PEF flag will not be automatically reset, it has to be cleared by the application program.

Timer/Event Counter Interrupt

For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the

corresponding timer interrupt enable bit, ET0I or ET1I, must first be set. An actual Timer/Event

Counter interrupt will take place when the Timer/Event Counter request flag, T0F or T1F, is set, a

situation that will occur when the Timer/Event Counter overflows. When the interrupt is enabled, the

stack is not full and a Timer/Event Counter overflow occurs, a subroutine call to the timer interrupt

vector at location 0CH or 10H, will take place. When the interrupt is serviced, the timer interrupt

request flag, T0F or T1F, will be automatically reset and the EMI bit will be automatically cleared to

disable other interrupts.

HT45F23/HT45F43

8-Bit Flash MCU with Op Amps & Comparators

Rev. 1.20

119

September 15, 2011

HT45F43 Datasheet(PDF) 119 Page - Holtek Semiconductor Inc

HT45F43 Datasheet(HTML) 119 Page - Holtek Semiconductor Inc

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