SPC56EC64L8 datasheet(65/118 Pages) STMICROELECTRONICS

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SPC564Bxx - SPC56ECxx

Electrical Characteristics

Doc ID 17478 Rev 4

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The internal voltage regulator requires external bulk capacitance (CREGn) to be connected

to the device to provide a stable low voltage digital supply to the device. Also required for

stability is the CDEC2 capacitor at ballast collector. This is needed to minimize sharp

injection current when ballast is turning ON. Apart from the bulk capacitance, user should

connect EMI/decoupling cap (CREGP) at each VDD_LV/VSS_LV pin pair.

Recommendations

●

The external NPN driver must be BCP68 type.

●

VDD_LV should be implemented as a power plane from the emitter of the ballast

transistor.

●

μF capacitors should be connected to the 4 pins closest to the outside of the

package and should be evenly distributed around the package. For BGA packages, the

balls should be used are D8, H14, R9, J3–one cap on each side of package.

–

There should be a track direct from the capacitor to this pin (pin also connects to

VDD_LV plane). The tracks ESR should be less than 100 mΩ.

–

The remaining VDD_LV pins (exact number will vary with package) should be

decoupled with 0.1

μF caps, connected to the pin as per 10 μF.

(see Section 4.4: Recommended operating conditions).

4.8.2

VDD_BV options

●

Option 1: VDD_BV shared with VDD_HV_A

VDD_BV must be star routed from VDD_HV_A from the common source. This is to

eliminate ballast noise injection on the MCU.

●

Option 2: VDD_BV independent of the MCU supply

VDD_BV > 2.6 V for correct functionality. The device is not monitoring this supply hence

the external component must meet the 2.6 V criteria through external monitoring if

required.

Table 23.

Voltage regulator electrical characteristics

Symbol

Parameter

Conditions(1)

Value(2)

Unit

Min

Typ

Max

CREGn

SR — External ballast stability capacitance

—

μF

RREG

SR —

Stability capacitor equivalent serial

resistance

——

—

0.2

CREGP

SR —

Decoupling capacitance (Close to

the pin)

VDD_HV_A/HV_B/VSS_HV

pair

100

—

VDD_LV/VSS_LV pair

100

—

CDEC2

SR —

Stability capacitance regulator

supply (Close to the ballast

collector)

VDD_HV_A/VSS_HV

—

μF

VMREG

CC P Main regulator output voltage

Before trimming

—

1.32

—

After trimming

—

1.28

—

IMREG

SR —

Main regulator current provided to

VDD_LV domain

——

—

350

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