SPC56EC64L8 datasheet(92/118 Pages) STMICROELECTRONICS

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Electrical Characteristics

SPC564Bxx - SPC56ECxx

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Doc ID 17478 Rev 4

4.18

Fast Ethernet Controller

MII signals use CMOS signal levels compatible with devices operating at 3.3 V. Signals are

not TTL compatible. They follow the CMOS electrical characteristics.

4.18.1

MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)

The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%.

There is no minimum frequency requirement. In addition, the system clock frequency must

exceed four times the RX_CLK frequency in 2:1 mode and two times the RX_CLK frequency

in 1:1 mode.

Figure 21. MII receive signal timing diagram

4.18.2

MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%.

There is no minimum frequency requirement. In addition, the system clock frequency must

VAINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the

conversion will be clamped respectively to 0x000 or 0xFFF.

During the sample time the input capacitance CS can be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the end of

the sample time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values for the

sample clock tADC1_S depend on programming.

Conversion time = Bit evaluation time + Sampling time + 1 Clock cycle delay.

Refer to ADC conversion table for detailed calculations.

Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a

combination of Offset, Gain and Integral Linearity errors.

Table 45.

MII Receive Signal Timing

Spec

Characteristic

Min

Max

Unit

RXD[3:0], RX_DV, RX_ER to

RX_CLK setup

5—

RX_CLK to RXD[3:0], RX_DV,

RX_ER hold

5—

RX_CLK pulse width high

35%

65%

RX_CLK period

RX_CLK pulse width low

35%

65%

RX_CLK period

RX_CLK (input)

RXD[3:0] (inputs)

RX_DV

RX_ER

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