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HT45F12 Datasheet(PDF) 16 Page - Holtek Semiconductor Inc |
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HT45F12 Datasheet(HTML) 16 Page - Holtek Semiconductor Inc |
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16 / 104 page ![]() Rev. 0.00 1� �e�te��e� ��� �01� Rev. 0.00 17 �e�te��e� ��� �01� HT45F12 8-Bit Flash MCU with Op Amps & Comparators HT45F12 8-Bit Flash MCU with Op Amps & Comparators System Architecture Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed totheirinternalsystemarchitecture.Therangeofdevicestakeadvantageoftheusualfeaturesfound withinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance. Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstruction executionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withthe exceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionset operations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement, branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulator andtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectly orindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditional architecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovidea functionalI/Owithmaximumreliabilityandflexibility.Thismakesthedevicesuitableforlow-cost, high-volumeproductionforcontrollerapplications Clocking and Pipelining Thesystemclock,derivedfromeitheraCrystal/ResonatororRCoscillatorissubdividedintofour internallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthe beginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4 clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleforms oneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutive instructioncycles,thepipeliningstructureofthemicrocontrollerensuresthatinstructionsare effectivelyexecutedinoneinstructioncycle.Theexceptiontothisareinstructionswherethe contentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasethe instructionwilltakeonemoreinstructioncycletoexecute. Forinstructionsinvolvingbranches,suchasjumporcallinstructions,twoinstructioncyclesare requiredtocompleteinstructionexecution.Anextracycleisrequiredastheprogramtakesone cycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethe branch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintiming sensitiveapplications. Fe tc h In st . ( PC ) Ex ec ut e In st . (P C- 1) Fe tc h In st . (P C+ 1) Ex ec ut e In st . (P C) Fe tc h In st . (P C+ 2) Ex ec ut e In st . (P C+ 1) PC PC +1 PC +2 O sci ll at or C lo ck (S yst em C lo ck) P has e Cl o ck T 1 Pr og ra m C oun te r P has e Cl o ck T 2 P has e Cl o ck T 3 P has e Cl o ck T 4 Pi pe lin in g System Clocking and Pipelining |
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