PXR40 datasheet(67/100 Pages) FREESCALE

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Electrical characteristics

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

6 This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the

synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal

startup time.

For Flexray operation, duty cycle requirements are higher.

8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

sys.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the Cjitter

percentage for a given interval. D_CLKOUT divider set to divide-by-2.

9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C

jitter +Cmod.

10 Modulation depth selected must not result in f

pll value greater than the fpll maximum specified value.

11 Maximum and minimum variation from programmed modulation depth is pending characterization. Depth settings available in

control register are: 2%, 3%, and 4% peak-to-peak.

12 Depth tolerance is the programmed modulation depth ±0.25% of F

sys. Violating the VCO min/max range may prevent the

system from exiting reset.

13 Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz

will result in reduced calibration accuracy.

14 Violating this range will cause the VCO max/min range to be violated with the default MFD settings out of reset.

Table 16. Oscillator electrical specifications1

(VDDSYN = 3.0 V to 3.6 V, VSS =VSSSYN =0 V, TA =TL to TH)

1 All values given are initial design targets and subject to change.

Spec

Characteristic

Symbol

Min

Max

Unit

Crystal Mode Differential Amplitude2

(Min differential voltage between EXTAL and XTAL)

2 This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode.

In that case, Vextal –Vxtal  400 mV criterion has to be met for oscillator’s comparator to produce output clock.

Vcrystal_diff_amp

| Vextal – Vxtal | > 0.4 V

—V

Crystal Mode: Internal Differential Amplifier Noise

Rejection

crystal_diff_amp_nr

—

| Vextal – Vxtal | < 0.2 V

EXTAL Input High Voltage

Bypass mode, External Reference

VIHEXT

((VDD33/2) + 0.4 V)

—V

EXTAL Input Low Voltage

Bypass mode, External Reference

VILEXT

—

(VDD33/2) – 0.4 V

XTAL Current3

3 I

xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.

IXTAL

Total On-chip stray capacitance on XTAL

CS_XTAL

—

1.5

Total On-chip stray capacitance on EXTAL

CS_EXTAL

—

1.5

Crystal manufacturer’s recommended capacitive load

See crystal spec

Discrete load capacitance to be connected to EXTAL

CL_EXTAL

—

(2 × CL –CS_EXTAL

–CPCB_EXTAL

)

4 C

PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.

Discrete load capacitance to be connected to XTAL

CL_XTAL

—

(2 × CL –CS_XTAL

–CPCB_XTAL

)

PXR40 Datasheet(PDF) 67 Page - Freescale Semiconductor, Inc

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