PXR40 datasheet(74/100 Pages) FREESCALE

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PXR40 Microcontroller Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

5.11.2

Pad AC specifications

2 Up to the maximum frequency rating of the device (refer to Table 39). The f

sys speed is the nominal maximum frequency.

270 Mhz parts allow for 264 Mhz system clock + 2% FM.

3 See the PXR40 Reference Manual for full description as not all bit combinations are valid.

4 EBI/Calibration bus is not available in all packages.

5 The EBI/Calibration Bus operating frequency, f

ebi_cal , depends on clock divider settings of block’s max allowed

frequency of operation. Normally febi_cal =fplatf /2, but can be limited to < fplatf /2 in Full Mode.

Table 26. IPCLKDIV settings

SIU_SYSDIV

[IPCLKDIV[0:1]]

Mode

Description

Enhanced

CPU frequency is doubled (Max 264Mhz). Platform,

peripheral, and eTPU clocks are 1/2 of CPU frequency

Full

CPU and eTPU frequency is doubled (Max 200Mhz).

Platform and peripheral clocks are 1/2 of CPU frequency.

—

Reserved

Legacy

CPU, eTPU, platform, and peripheral’s clocks all run at

same speed (Max 132Mhz).

Table 27. SYSCLKDIV settings

SIU_SYSDIV

[SYSCLKDIV[0:1]]

Description

Divide by 2.

Divide by 4.

Divide by 8.

Divide by 16.

Table 28. Pad AC specifications (vddeh = 5.0 V, VDDE =3.3 V)

Spec

Pad

SRC/DSC

Out Delay2,4

 H/H  L (ns)

Rise/Fall3,4

(ns)

Load Drive

(pF)

1Medium5

152/165

70/74

205/220

96/96

200

28/34

12/15

52/59

28/31

200

12/12

5.3/5.9

32/32

22/22

200

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