PXR40 datasheet(85/100 Pages) FREESCALE

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Electrical characteristics

PXR40 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Figure 19. D_CLKOUT timing

Input Signal Valid to D_CLKOUT

Posedge (Setup Time)

D_ADD[9:30]

D_DAT[0:15]

D_RD_WR

D_TA

D_TS

tCIS

5.0/4.5

—

Input setup time selectable via

SIU_ECCR[EBTS] bit:

EBTS = 0; 5.0ns

EBTS = 1; 4.5ns

D_CLKOUT Posedge to Input

Signal Invalid (Hold Time)

D_ADD[9:30]

D_DAT[0:15]

D_RD_WR

D_TA

D_TS

tCIH

1.0

—

D_ALE Pulse Width

tAPW

6.5

—

The timing is for Asynchronous

external memory system.

D_ALE Negated to Address Invalid

tAAI

2.0/1.0 5

—

The timing is for Asynchronous

external memory system.

ALE is measured at 50% of VDDE.

1 EBI timing specified at V

DD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA =TL to TH, and

CL = 30 pF with DSC = 0b10.

2 Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).

270 MHz parts allow for 264 MHz system clock + 2% FM.

3 Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum external bus frequency.

The maximum external bus frequency is 66 MHz.

4 Refer to Fast pad timing in Table 28 and Table 29.

5 ALE hold time spec is temperature dependant. 1.0 ns spec applies for temperature range -40 to 0

C. 2.0 ns spec applies to

temperatures > 0

C. This spec has no dependency on SIU_ECCR[EBTS] bit.

Table 33. Bus operation timing 1 (continued)

Spec

Characteristic

Symbol

66 MHz (Ext. Bus Freq)2 3

Unit

Notes

Min

Max

D_CLKOUT

VDDE / 2

VOL_F

VOH_F

PXR40 Datasheet(PDF) 85 Page - Freescale Semiconductor, Inc

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