ACT8600 datasheet(34/50 Pages) ACTIVE-SEMI

34 / 50 page

ACT8600

Rev 3, 15-Nov-12

Innovative Power

ActivePMU

TM and ActivePathTM are trademarks of Active-Semi.

2CTM is a trademark of NXP.

- 34 -

www.active-semi.com

The ACT8600 is optimized for use in applications

using the Ingenic JZ4770 processor, supporting

both the power domains as well as the signal

interface for these processors.

The following paragraphs describe how to design

ACT8600 with JZ4770 processor.

While the ACT8600 supports many possible

configurations for powering these processors, one

of the most common configurations is detailed in

this datasheet.

Control Signals

Master Enable (PWREN) Input

PWREN is a logic input which turns ON REG1,

REG2, REG3, and REG5 when asserted. All

regulators except the RTC LDOs (REG9) will be

turned OFF when PWREN is de-asserted.

nRSTO Output

The power on reset pin, nRSTO is an open-drain

output. Connect a 10kΩ or greater pull-up resistor

from nRSTO to REG9.

- The nRSTO output pin is asserted low only when

the REG9 voltage is below 1.67V

- If REG1 is above its power-OK threshold when

the reset timer (40ms) expires, nRSTO is de-

asserted.

nIRQ Output

nIRQ is an open-drain output that asserts low any

time an interrupt is generated. Connect a 10kΩ or

greater pull-up resistor from nIRQ to the I/O rail.

nIRQ is typically used to drive the interrupt input of

the system processor.

Many of the ACT8600's functions support interrupt-

generation as a result of various conditions. These

are typically masked by default, but may be

unmasked via the I2C interface. For more

information about the available fault conditions,

refer to the appropriate sections of this datasheet.

Power Control Sequences

When the VVSYS rises above the UVLO, or REG9

rises above 93% of its default value (in the case

when a charged backup battery is installed),

nRSTO is asserted low immediately and REG9 is

enabled. REG1, REG2 and REG3 will be enabled

when PWREN = 1 and VVSYS is above 3.45V. When

REG1 reaches 93% of the default value, REG5 will

be enabled, and nRSTO is de-asserted after a

40ms delay.

Once the system is turned ON, the processor may

shut down the system by pulling down PWREN. In

that case, all of the regulators, except REG9 will be

turned off (REG9 is the always ON LDO). When

PWREN is pulled high again, OUT1/2/3/5 will be

turned ON again but nRSTO remains de-asserted

as long as REG9 is within regulation.

SYSTEM CONTROL INFORMATION

Interfacing with the Ingenic JZ4770 Processor

Table 1:

ACT8600 and Ingenic JZ4770 Power Domains

POWER DOMAIN ACT8600 CHANNEL

TYPE

DEFAULT VOLTAGE

CURRENT CAPABILITY

CPU Core

REG1

Step-Down DC/DC

1.2V

1200mA

IO / AVDAUD

REG2

Step-Down DC/DC

3.3V

1200mA

MEM

REG3

Step-Down DC/DC

1.8V

950mA

USB OTG

REG4

Step-Up DC/DC

600mA

AVD

REG5

LDO

2.5V

350mA

General Purpose

REG6

LDO

1.8V

350mA

General Purpose

REG7

LDO

1.8V

250mA

General Purpose

REG8

LDO

1.8V

250mA

VDDRTC

REG9

LDO

3.3V

5mA

VDDRTC12

REG10

LDO

1.2V

5mA

ACT8600 Datasheet(PDF) 34 Page - Active-Semi, Inc

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