ADV7180WBSTZ datasheet(60/120 Pages) AD

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ADV7180

Data Sheet

Rev. G | Page 60 of 120

I2C Interface

Dedicated I2C readback registers are available for CCAP, CGMS,

WSS, Gemstar, VPS, PDC/UTC, and VITC. Because teletext is a

high data rate standard, data extraction is supported only through

the ancillary data packet.

User Interface for I2C Readback Registers

The VDP decodes all enabled VBI data standards in real time.

Because the I2C access speed is much lower than the decoded

rate, when the registers are accessed, they may be updated with

data from the next line. To avoid this, VDP has a self-clearing

clear bit and an available (AVL) status bit accompanying all I2C

readback registers.

The user must clear the I2C readback register by writing a high to

the clear bit. This resets the state of the available bit to low and

indicates that the data in the associated readback registers is not

valid. After the VDP decodes the next line of the corresponding

VBI data, the decoded data is placed into the I2C readback

data is now available.

Though the VDP decodes this VBI data in subsequent lines if

present, the decoded data is not updated to the readback registers

until the clear bit is set high again. However, this data is

available through the 656 ancillary data packets.

The clear and available bits are in the VDP_STATUS_CLEAR

(0x78, user sub map, write only) and VDP_STATUS (0x78, user

sub map, read only) registers, respectively.

Example I2C Readback Procedure

The following tasks must be performed to read one packet

(line) of PDC data from the decoder:

1. Write 10 to I2C_GS_VPS_PDC_UTC[1:0] (0x9C, user sub

map) to specify that PDC data must be updated to I2C

registers.

2. Write high to the GS_PDC_VPS_UTC_CLEAR bit (0x78,

user sub map) to enable I2C register updating.

3. Poll the GS_PDC_VPS_UTC_AVL bit (0x78, user sub

map) going high to check the availability of the PDC

packets.

4. Read the data bytes from the PDC I2C registers. Repeat

Step 1 to Step 3 to read another line or packet of data.

To read a packet of CCAP, CGMS, or WSS data, Step 1 to Step 3

are required only because they have dedicated registers.

VDP—Content-Based Data Update

For certain standards, such as WSS, CGMS, Gemstar, PDC, UTC,

and VPS, the information content in the signal transmitted remains

the same over numerous lines, and the user may want to be notified

only when there is a change in the information content or loss of

the information content. The user must enable content-based

updating for the required standard through the GS_VPS_PDC_

UTC_CB_CHANGE and WSS_CGMS_CB_CHANGE bits.

Therefore, the available bit shows the availability of that

standard only when its content has changed.

Content-based updating also applies to lines with lost data.

Therefore, for standards like VPS, Gemstar, CGMS, and WSS, if no

data arrives in the next four lines programmed, the corresponding

available bit in the VDP_STATUS register is set high and the

content in the I2C registers for that standard is set to 0. The user

must write high to the corresponding clear bit so that when a

valid line is decoded after some time, the decoded results are

available in the I2C registers, with the available status bit set high.

If content-based updating is enabled, the available bit is set high

(assuming the clear bit was written) in the following cases:

•

The data contents have changed.

•

Data was being decoded and four lines with no data have

been detected.

•

No data was being decoded and new data is now being

decoded.

GS_VPS_PDC_UTC_CB_CHANGE, Enable Content-

Based Updating for Gemstar/VPS/PDC/UTC,

Address 0x9C[5], User Sub Map

Setting GS_VPS_PDC_UTC_CB_CHANGE to 0 disables

content-based updating.

Setting GS_VPS_PDC_UTC_CB_CHANGE to 1 (default)

enables content-based updating.

WSS_CGMS_CB_CHANGE, Enable Content-Based

Updating for WSS/CGMS, Address 0x9C[4],

User Sub Map

Setting WSS_CGMS_CB_CHANGE to 0 disables content-based

updating.

Setting WSS_CGMS_CB_CHANGE to 1 (default) enables

content-based updating.

VDP—Interrupt-Based Reading of VDP I2C Registers

Some VDP status bits are also linked to the interrupt request

controller so that the user does not have to poll the available status

bit. The user can configure the video decoder to trigger an

interrupt request on the INTRQ pin in response to the valid

data available in the I2C registers. This function is available for

the following data types:

•

CGMS or WSS. The user can select either triggering an

interrupt request each time sliced data is available or

triggering an interrupt request only when the sliced data

has changed. Selection is made via the WSS_CGMS_CB_

CHANGE bit.

•

Gemstar, PDC, VPS, or UTC. The user can select to trigger

an interrupt request each time sliced data is available or to

trigger an interrupt request only when the sliced data has

changed. Selection is made via the GS_VPS_PDC_UTC_

CB_CHANGE bit.

ADV7180WBSTZ Datasheet(PDF) 60 Page - Analog Devices

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