ADV7180WBSTZ datasheet(77/120 Pages) AD

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Data Sheet

ADV7180

Rev. G | Page 77 of 120

MPU PORT DESCRIPTION

The ADV7180 supports a 2-wire (I2C-compatible) serial interface.

Two inputs, serial data (SDATA) and serial clock (SCLK), carry

information between the ADV7180 and the system I2C master

controller. Each slave device is recognized by a unique address.

The ADV7180 I2C port allows the user to set up and configure

the decoder and to read back the captured VBI data. The

ADV7180 has four possible slave addresses for both read and

write operations, depending on the logic level of the ALSB pin.

The four unique addresses are shown in Table 104. The ADV7180

ALSB pin controls Bit 1 of the slave address. By altering the

ALSB, it is possible to control two ADV7180s in an application

without the conflict of using the same slave address. The LSB

(Bit 0) sets either a read or write operation. Logic 1 corresponds to

a read operation, and Logic 0 corresponds to a write operation.

Table 104. I2C Address for ADV7180

ALSB

R/W

Slave Address

0x40

0x41

0x42

0x43

To control the device on the bus, a specific protocol must be

followed. First, the master initiates a data transfer by establishing a

start condition, which is defined by a high-to-low transition on

SDATA while SCLK remains high. This indicates that an address/

data stream follows. All peripherals respond to the start condition

and shift the next eight bits (the 7-bit address plus the R/W bit).

The bits are transferred from MSB down to LSB. The peripheral

that recognizes the transmitted address responds by pulling the

data line low during the ninth clock pulse; this is known as an

acknowledge bit. All other devices withdraw from the bus at

this point and maintain an idle condition. The idle condition is

where the device monitors the SDATA and SCLK lines for the

start condition and the correct transmitted address. The R/W

bit determines the direction of the data. Logic 0 on the LSB of

the first byte means that the master writes information to the

peripheral. Logic 1 on the LSB of the first byte means that the

master reads information from the peripheral.

The ADV7180 acts as a standard slave device on the bus. The

data on the SDATA pin is eight bits long, supporting the 7-bit

address plus the R/W bit. The device has 249 subaddresses to

enable access to the internal registers. It, therefore, interprets

the first byte as the device address and the second byte as the

starting subaddress. The subaddresses auto-increment, allowing

data to be written to or read from the starting subaddress. A data

transfer is always terminated by a stop condition. The user can

also access any unique subaddress register on a one-by-one

basis without updating all the registers.

Stop and start conditions can be detected at any stage during the

data transfer. If these conditions are asserted out of sequence with

normal read and write operations, they cause an immediate jump

to the idle condition. During a given SCLK high period, the user

should only issue one start condition, one stop condition, or a

single stop condition followed by a single start condition. If an

invalid subaddress is issued by the user, the ADV7180 does not

issue an acknowledge and returns to the idle condition.

In auto-increment mode, if the user exceeds the highest

subaddress, the following action is taken:



In read mode, the highest subaddress register contents

continue to be output until the master device issues a

no acknowledge. This indicates the end of a read. A no

acknowledge condition occurs when the SDATA line is

not pulled low on the ninth pulse.



In write mode, the data for the invalid byte is not loaded

into any subaddress register. A no acknowledge is issued by

the ADV7180, and the part returns to the idle condition.

SDATA

SCLK

START ADDR

ACK

DATA

ACK

STOP

SUBADDRESS

1–7

R/W

Figure 51. Bus Data Transfer

WRITE

SEQUENCE

SLAVE ADDR A(S)

SUB ADDR

A(S)

DATA

A(S)

DATA

A(S) P

READ

SEQUENCE

SLAVE ADDR

A(S)

SUB ADDR

A(S) S

A(S)

DATA

A(M)

DATA

A(M) P

S = START BIT

P= STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A(S) = NO ACKNOWLEDGE BY SLAVE

A(M) = NO ACKNOWLEDGE BY MASTER

LSB = 1

LSB = 0

Figure 52. Read and Write Sequence

ADV7180WBSTZ Datasheet(PDF) 77 Page - Analog Devices

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