MPC8241EC datasheet(43/58 Pages) FREESCALE

43 / 58 page

MPC8241 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

System Design Information

Place the circuits as closely as possible to the respective input signal pins to minimize noise coupled from

nearby circuits. Routing from the capacitors to the input signal pins should be as direct as possible with

minimal inductance of vias.

Figure 26. PLL Power Supply Filter Circuit

7.2

Decoupling Recommendations

Dynamic power management, large address and data buses, and high operating frequencies enable the

MPC8241 to generate transient power surges and high frequency noise in its power supply, especially

while driving large capacitive loads. This noise must be prevented from reaching other components in the

MPC8241 system, and the MPC8241 itself requires a clean, tightly regulated source of power. Therefore,

place at least one decoupling capacitor at each VDD, GVDD_OVDD, and LVDD pin. These decoupling

capacitors receive their power from dedicated power planes in the PCB, using short traces to minimize

inductance. These capacitors should have a value of 0.1 µF. To minimize lead inductance, use only ceramic

SMT (surface mount technology) capacitors, preferably 0508 or 0603, on which connections are made

along the length of the part.

In addition, distribute several bulk storage capacitors around the PCB to feed the VDD, GVDD_OVDD, and

LVDD planes and enable quick recharging of the smaller chip capacitors. These bulk capacitors should

have a low ESR (equivalent series resistance) rating to ensure the necessary quick response time, and

should be connected to the power and ground planes through two vias to minimize inductance. Freescale

recommends using bulk capacitors: 100–330 µF (AVX TPS tantalum or Sanyo OSCON).

7.3

Connection Recommendations

To ensure reliable operation, connect unused inputs to an appropriate signal level. Tie unused active-low

inputs to OVDD. Connect unused active-high inputs to GND. All no connect (NC) signals must remain

unconnected.

Power and ground connections must be made to all external VDD, GVDD_OVDD, LVDD, and GND pins.

The PCI_SYNC_OUT signal is to be routed halfway out to the PCI devices and then returned to the

PCI_SYNC_IN input.

The SDRAM_SYNC_OUT signal is to be routed halfway out to the SDRAM devices and then returned to

the SDRAM_SYNC_IN input of the MPC8241. The trace length can be used to skew or adjust the timing

window as needed. See the Tundra Tsi107™ Design Guide (AN1849) and Freescale application notes

AN2164/D, MPC8245/MPC8241 Memory Clock Design Guidelines: Part 1 and AN2746,

MPC8245/MPC8241 Memory Clock Design Guidelines: Part 2 for more details. Note the

SDRAM_SYNC_IN to PCI_SYNC_IN time requirement (see Table 10).

VDD

AVDD or AVDD2

2.2 µF

GND

Low ESL Surface Mount Capacitors

MPC8241EC Datasheet(PDF) 43 Page - Freescale Semiconductor, Inc

MPC8241EC Datasheet(HTML) 43 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

Datasheet Download

Link URL