M68ICS08GR datasheet(203/408 Pages) FREESCALE

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Monitor ROM (MON)

Security

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Monitor ROM (MON)

203

Figure 15-8. Monitor Mode Entry Timing

Upon power-on reset, if the received bytes of the security code do not

match the data at locations $FFF6–$FFFD, the host fails to bypass the

security feature. The MCU remains in monitor mode, but reading a

FLASH location returns an invalid value and trying to execute code from

FLASH causes an illegal address reset. After receiving the eight security

bytes from the host, the MCU transmits a break character, signifying that

it is ready to receive a command.

NOTE:

The MCU does not transmit a break character until after the host sends

the eight security bytes.

To determine whether the security code entered is correct, check to see

if bit 6 of RAM address $40 is set. If it is, then the correct security code

has been entered and FLASH can be accessed.

PA0

PA1

RST

VDD

4096 + 32 CGMXCLK CYCLES

24 BUS CYCLES

256 BUS CYCLES (MINIMUM)

NOTES:

2 = Data return delay, 2 bit times

4 = Wait 1 bit time before sending next byte.

FROM HOST

FROM MCU

1 = Echo delay, 2 bit times

Freescale Semiconductor, Inc.

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M68ICS08GR Datasheet(PDF) 203 Page - Freescale Semiconductor, Inc