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M68ICS08GR Datasheet(PDF) 202 Page - Freescale Semiconductor, Inc |
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M68ICS08GR Datasheet(HTML) 202 Page - Freescale Semiconductor, Inc |
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202 / 408 page ![]() Monitor ROM (MON) Technical Data MC68HC908GR8 — Rev 4.0 202 Monitor ROM (MON) MOTOROLA The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at addresses SP +5 and SP +6. Figure 15-7. Stack Pointer at Monitor Mode Entry 15.5 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user- defined data. NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons, they should be programmed even if they are not used for vectors. During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PTA0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the security feature and can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. (See Figure 15-8.) CONDITION CODE REGISTER ACCUMULATOR LOW BYTE OF INDEX REGISTER HIGH BYTE OF PROGRAM COUNTER LOW BYTE OF PROGRAM COUNTER SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP SP + 6 HIGH BYTE OF INDEX REGISTER SP + 7 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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