M68ICS08GR datasheet(106/408 Pages) FREESCALE

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Clock Generator Module (CGMC)

Technical Data

MC68HC908GR8 — Rev 4.0

106

Clock Generator Module (CGMC)

MOTOROLA

•

Software must wait a given time, tAL, after entering tracking mode

before selecting the PLL as the clock source to CGMOUT

(BCS = 1).

•

The LOCK bit is disabled.

•

CPU interrupts from the CGMC are disabled.

7.4.6 Programming the PLL

The following procedure shows how to program the PLL.

NOTE:

The round function in the following equations means that the real

number should be rounded to the nearest integer number.

1. Choose the desired bus frequency, fBUSDES.

2. Calculate the desired VCO frequency (four times the desired bus

frequency).

3. Choose a practical PLL (crystal) reference frequency, fRCLK, and

the reference clock divider, R. Typically, the reference crystal is

32.768 kHz and R = 1.

Frequency errors to the PLL are corrected at a rate of fRCLK/R. For

stability and lock time reduction, this rate must be as fast as

possible. The VCO frequency must be an integer multiple of this

rate. The relationship between the VCO frequency, fVCLK, and the

reference frequency, fRCLK, is

P, the power of two multiplier, and N, the range multiplier, are

integers.

In cases where desired bus frequency has some tolerance,

choose fRCLK to a value determined either by other module

requirements (such as modules which are clocked by CGMXCLK),

cost requirements, or ideally, as high as the specified range

VC LKD ES

BUSDES

VCLK

----------- f

RCLK

()

Freescale Semiconductor, Inc.

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