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DSPIC33FJ06GS201TE/MM Datasheet(PDF) 197 Page - Microchip Technology |
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DSPIC33FJ06GS201TE/MM Datasheet(HTML) 197 Page - Microchip Technology |
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197 / 346 page  © 2009 Microchip Technology Inc. Preliminary DS70318D-page 195 dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — —OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0 — — — OCFLT OCTSEL OCM<2:0> bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Stop Output Compare in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode bit 12-5 Unimplemented: Read as ‘0’ bit 4 OCFLT: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in hardware only) 0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111) bit 3 OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for Compare x 0 = Timer2 is the clock source for Compare x bit 2-0 OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx, Fault pin enabled 110 = PWM mode on OCx, Fault pin disabled 101 = Initialize OCx pin low, generate continuous output pulses on OCx pin 100 = Initialize OCx pin low, generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled |
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