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DSPIC33FJ06GS201TE/MM Datasheet(PDF) 213 Page - Microchip Technology |
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DSPIC33FJ06GS201TE/MM Datasheet(HTML) 213 Page - Microchip Technology |
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213 / 346 page ![]() © 2009 Microchip Technology Inc. Preliminary DS70318D-page 211 dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 bit 3-2 CLDAT<1:0>: Data for PWMxH and PWMxL Pins if CLMODE is Enabled bits FCLCONx<IFLTMOD> = 0: Normal Fault mode: If current-limit active, then CLDAT<1> provides data for PWMxH. If current-limit active, then CLDAT<0> provides data for PWMxL. FCLCONx<IFLTMOD> = 1: Independent Fault mode: CLDAT<1:0> is ignored. bit 1 SWAP<1:0>: SWAP PWMxH and PWMxL pins 1 = PWMxH output signal is connected to PWMxL pin and PWMxL signal is connected to PWMxH pins 0 = PWMxH and PWMxL pins are mapped to their respective pins bit 0 OSYNC: Output Override Synchronization bit 1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base 0 = Output overrides via the OVDDAT<1:0> bits occur on next CPU clock boundary REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER (CONTINUED) Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. |
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