DSPIC33FJ06GS201TESLASHMM datasheet(225/346 Pages) MICROCHIP

225 / 346 page

Preliminary

DS70318D-page 223

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

17.0

INTER-INTEGRATED CIRCUIT

(I2C™)

The Inter-Integrated Circuit (I2C) module provides

complete hardware support for both Slave and

Multi-Master modes of the I2C serial communication

standard with a 16-bit interface.

The I2C module has a 2-pin interface:

• The SCLx pin is clock.

• The SDAx pin is data.

The I2C module offers the following key features:

•I2C interface supporting both Master and Slave

modes of operation.

•I2C Slave mode supports 7-bit and

10-bit addressing.

•I2C Master mode supports 7-bit and

10-bit addressing.

•I2C port allows bidirectional transfers between

master and slaves.

• Serial clock synchronization for I2C port can be

used as a handshake mechanism to suspend and

resume serial transfer (SCLREL control).

•I2C supports multi-master operation, detects bus

collision and arbitrates accordingly.

17.1

Operating Modes

The hardware fully implements all the master and slave

functions of the I2C Standard and Fast mode

specifications, as well as 7-bit and 10-bit addressing.

The I2C module can operate either as a slave or a

master on an I2C bus.

The following types of I2C operation are supported:

•I2C slave operation with 7-bit addressing

•I2C slave operation with 10-bit addressing

•I2C master operation with 7-bit or 10-bit addressing

For details about the communication sequence in each

of these modes, refer to the “dsPIC33F Family

Reference Manual

”. Please see the Microchip web site

(www.microchip.com) for the latest “dsPIC33F Family

Reference Manual

” chapters.

17.2

I2C Registers

I2CxCON and I2CxSTAT are control and status

registers, respectively. The I2CxCON register is

readable and writable. The lower six bits of I2CxSTAT

are read-only. The remaining bits of the I2CSTAT are

read/write:

• I2CxRSR is the shift register used for shifting data

internal to the module and the user application

has no access to it.

• I2CxRCV is the receive buffer and the register to

which data bytes are written, or from which data

bytes are read.

• I2CxTRN is the transmit register to which bytes

are written during a transmit operation.

• The I2CxADD register holds the slave address.

• A status bit, ADD10, indicates 10-Bit Address

mode.

• The I2CxBRG acts as the Baud Rate Generator

(BRG) reload value.

In receive operations, I2CxRSR and I2CxRCV together

form a double-buffered receiver. When I2CxRSR

receives a complete byte, it is transferred to I2CxRCV,

and an interrupt pulse is generated.

Note:

This data sheet summarizes the features

the

dsPIC33FJ06GS101/X02

and

dsPIC33FJ16GSX02/X04

families

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to the “dsPIC33F Family

Reference

Manual”

Section

19.

“Inter-Integrated

Circuit

(I2C™)”

(DS70195), which is available on the

Microchip web site (www.microchip.com).

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