DSPIC33FJ06GS201TESLASHMM datasheet(227/346 Pages) MICROCHIP

227 / 346 page

Preliminary

DS70318D-page 225

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

I2CxCON: I2Cx CONTROL REGISTER

R/W-0

U-0

R/W-0

R/W-1, HC

R/W-0

I2CEN

—

I2CSIDL

SCLREL

IPMIEN

A10M

DISSLW

SMEN

bit 15

bit 8

R/W-0

R/W-0, HC

GCEN

STREN

ACKDT

ACKEN

RCEN

PEN

RSEN

SEN

bit 7

bit 0

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

W = Writable bit

HS = Hardware Settable bit

HC = Hardware Clearable bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

I2CEN:

I2Cx Enable bit

= Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins

= Disables the I2Cx module. All I2C pins are controlled by port functions.

bit 14

Unimplemented:

Read as ‘0’

bit 13

I2CSIDL:

Stop in Idle Mode bit

= Discontinue module operation when device enters an Idle mode

= Continue module operation in Idle mode

bit 12

SCLREL:

SCLx Release Control bit (when operating as I2C slave)

= Release SCLx clock

= Hold SCLx clock low (clock stretch)

If STREN = 1:

Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear

at beginning of slave transmission. Hardware clear at end of slave reception.

If STREN = 0:

Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave

transmission.

bit 11

IPMIEN:

Intelligent Peripheral Management Interface (IPMI) Enable bit

= IPMI mode is enabled; all addresses acknowledged

= IPMI mode disabled

bit 10

A10M:

10-Bit Slave Address bit

= I2CxADD is a 10-bit slave address

= I2CxADD is a 7-bit slave address

bit 9

DISSLW:

Disable Slew Rate Control bit

= Slew rate control disabled

= Slew rate control enabled

bit 8

SMEN:

SMbus Input Levels bit

= Enable I/O pin thresholds compliant with SMbus specification

= Disable SMbus input thresholds

bit 7

GCEN:

General Call Enable bit (when operating as I2C slave)

= Enable interrupt when a general call address is received in the I2CxRSR

(module is enabled for reception)

= General call address disabled

bit 6

STREN:

SCLx Clock Stretch Enable bit (when operating as I2C slave)

Used in conjunction with SCLREL bit.

= Enable software or receive clock stretching

= Disable software or receive clock stretching

DSPIC33FJ06GS201TE/MM Datasheet(PDF) 227 Page - Microchip Technology

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