DSPIC33FJ06GS201TESLASHMM datasheet(139/346 Pages) MICROCHIP

139 / 346 page

Preliminary

DS70318D-page 137

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

8.1.3

PLL CONFIGURATION

The primary oscillator and internal FRC oscillator can

optionally use an on-chip PLL to obtain higher speeds

of operation. The PLL provides significant flexibility in

selecting the device operating speed. A block diagram

of the PLL is shown in Figure 8-2.

The output of the primary oscillator or FRC, denoted as

‘FIN’, is divided down by a prescale factor (N1) of 2, 3,

... or 33 before being provided to the PLL’s Voltage

Controlled Oscillator (VCO). The input to the VCO must

be selected in the range of 0.8 MHz to 8 MHz. The

prescale

factor

‘N1’

selected

using

the

PLLPRE<4:0> bits (CLKDIV<4:0>).

The PLL Feedback Divisor, selected using the

PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor, ‘M’,

by which the input to the VCO is multiplied. This factor

must be selected such that the resulting VCO output

frequency is in the range of 100 MHz to 200 MHz.

The VCO output is further divided by a postscale factor,

‘N2’. This factor is selected using the PLLPOST<1:0>

bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4, or 8, and

must be selected such that the PLL output frequency

(FOSC) is in the range of 12.5 MHz to 80 MHz, which

generates device operating speeds of 6.25-40 MIPS.

For a primary oscillator or FRC oscillator, output ‘FIN’,

the PLL output ‘FOSC’ is given by Equation 8-2.

EQUATION 8-2:

FOSC CALCULATION

For example, suppose a 10 MHz crystal is being used

with the selected oscillator mode of XT with PLL (see

Equation 8-3).

• If PLLPRE<4:0> = 0, then N1 = 2. This yields a

VCO input of 10/2 = 5 MHz, which is within the

acceptable range of 0.8-8 MHz.

• If PLLDIV<8:0> = 0x1E, then M = 32. This yields a

VCO output of 5 x 32 = 160 MHz, which is within

the 100-200 MHz ranged needed.

• If PLLPOST<1:0> = 0, then N2 = 2. This provides

a Fosc of 160/2 = 80 MHz. The resultant device

operating speed is 80/2 = 40 MIPS.

EQUATION 8-3:

XT WITH PLL MODE

EXAMPLE

FIGURE 8-2:

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PLL BLOCK DIAGRAM

8.2

Auxiliary Clock Generation

The auxiliary clock generation is used for a peripherals

that need to operate at a frequency unrelated to the

system clock such as a PWM or ADC.

The primary oscillator and internal FRC oscillator

sources can be used with an auxiliary PLL to obtain the

auxiliary clock. The auxiliary PLL has a fixed 16x

multiplication factor.

8.3

Reference Clock Generation

The reference clock output logic provides the user with

the ability to output a clock signal based on the system

clock or the crystal oscillator on a device pin. The user

application can specify a wide range of clock scaling

prior to outputting the reference clock.

(

)

N1*N2

FOSC = FIN *

FCY =

FOSC

(

10000000 * 32

2 * 2

) 40 MIPS

0.8-8.0 MHz

Here(1)

100-200 MHz

Here(1)

Divide by

2, 4, 8

Divide by

2-513

Divide by

2-33

Source (Crystal, External

PLLPRE

VCO

PLLDIV

PLLPOST

Clock or Internal RC)

12.5-80 MHz

Here(1)

FOSC

FVCO

Note 1:

This frequency range must be satisfied at all times.

Note:

To achieve 1.04 ns PWM resolution, the

auxiliary clock must be set up for 120 MHz.

Note:

If the primary PLL is used as a source for

the auxiliary clock, then the primary PLL

should be configured up to a maximum

operation of 30 MIPS or less.

DSPIC33FJ06GS201TE/MM Datasheet(PDF) 139 Page - Microchip Technology

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