DSPIC33FJ06GS201TESLASHMM datasheet(145/346 Pages) MICROCHIP

145 / 346 page

Preliminary

DS70318D-page 143

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER

R/W-0

R-0

R/W-0

U-0

R/W-0

ENAPLL

APLLCK

SELACLK

—

APSTSCLR<2:0>

bit 15

bit 0

R/W-0

U-0

ASRCSEL

FRCSEL

—

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

ENAPLL:

Auxiliary PLL Enable bit

= APLL is enabled

= APLL is disabled

bit 14

APLLCK:

APLL Locked Status bit (read-only)

= Indicates that auxiliary PLL is in lock

= Indicates that auxiliary PLL is not in lock

bit 13

SELACLK:

Select Auxiliary Clock Source for Auxiliary Clock Divider bit

= Auxiliary Oscillators provides the source clock for auxiliary clock divider

= Primary PLL (FVCO) provides the source clock for auxiliary clock divider

bit 12-11

Unimplemented:

Read as ‘0’

bit 10-8

APSTSCLR<2:0>:

Auxiliary Clock Output Divider bits

111

= Divided by 1

110

= Divided by 2

101

= Divided by 4

100

= Divided by 8

011

= Divided by 16

010

= Divided by 32

001

= Divided by 64

000

= Divided by 256

bit 7

ASRCSEL:

Select Reference Clock Source for Auxiliary Clock bit

= Primary oscillator is the clock source

= No clock input is selected

bit 6

FRCSEL:

Select Reference Clock Source for Auxiliary PLL bit

= Select FRC clock for auxiliary PLL

= Input clock source is determined by ASRCSEL bit setting

bit 5-0

Unimplemented:

Read as ‘0’

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