DSPIC33FJ06GS201TESLASHMM datasheet(149/346 Pages) MICROCHIP

149 / 346 page

Preliminary

DS70318D-page 147

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

9.0

POWER-SAVING FEATURES

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/

X04 devices provide the ability to manage power

consumption by selectively managing clocking to the

CPU and the peripherals. In general, a lower clock

frequency and a reduction in the number of circuits being

clocked

constitutes

lower

consumed

power.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

devices can manage power consumption in four different

ways:

• Clock Frequency

• Instruction-Based Sleep and Idle modes

• Software-Controlled Doze mode

• Selective Peripheral Control in Software

Combinations of these methods can be used to

selectively tailor an application’s power consumption

while still maintaining critical application features, such

as timing-sensitive communications.

9.1

Clock Frequency and Clock

Switching

The

dsPIC33FJ06GS101/X02

and

dsPIC33FJ16GSX02/X04 devices allow a wide range

of clock frequencies to be selected under application

control. If the system clock configuration is not locked,

users can choose low-power or high-precision

oscillators by simply changing the NOSC bits

(OSCCON<10:8>). The process of changing a system

clock during operation, as well as limitations to the

process, are discussed in more detail in Section 8.0

“Oscillator Configuration”

9.2

Instruction-Based Power-Saving

Modes

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/

X04 devices have two special power-saving modes that

are entered through the execution of a special PWRSAV

instruction. Sleep mode stops clock operation and halts all

code execution. Idle mode halts the CPU and code

execution, but allows peripheral modules to continue

operation. The assembler syntax of the PWRSAV

instruction is shown in Example 9-1.

Sleep and Idle modes can be exited as a result of an

enabled interrupt, WDT time-out or a device Reset. When

the device exits these modes, it is said to wake-up.

9.2.1

SLEEP MODE

The following occur in Sleep mode:

• The system clock source is shut down. If an

on-chip oscillator is used, it is turned off.

• The device current consumption is reduced to a

minimum, provided that no I/O pin is sourcing

current.

• The Fail-Safe Clock Monitor does not operate,

since the system clock source is disabled.

• The LPRC clock continues to run in Sleep mode if

the WDT is enabled.

• The WDT, if enabled, is automatically cleared

prior to entering Sleep mode.

• Some device features or peripherals may continue

to operate. This includes the items such as the

input change notification on the I/O ports or

peripherals that use an external clock input.

• Any peripheral that requires the system clock

source for its operation is disabled.

The device will wake-up from Sleep mode on any of

these events:

• Any interrupt source that is individually enabled

• Any form of device Reset

• A WDT time-out

On wake-up from Sleep mode, the processor restarts

with the same clock source that was active when Sleep

mode was entered.

EXAMPLE 9-1:

PWRSAV

INSTRUCTION SYNTAX

Note:

This data sheet summarizes the features

the

dsPIC33FJ06GS101/X02

and

dsPIC33FJ16GSX02/X04

families

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to the “dsPIC33F Family

Reference

Manual”

Section

“Watchdog Timer and Power-Saving

Modes”

(DS70196), which is available

from the Microchip web site (www.micro-

chip.com).

Note:

SLEEP_MODE

and

IDLE_MODE

are

constants defined in the assembler

include file for the selected device.

PWRSAV

#SLEEP_MODE

; Put the device into SLEEP mode

PWRSAV

#IDLE_MODE

; Put the device into IDLE mode

DSPIC33FJ06GS201TE/MM Datasheet(PDF) 149 Page - Microchip Technology

DSPIC33FJ06GS201TE/MM Datasheet(HTML) 149 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL