DSPIC33FJ06GS201TESLASHMM datasheet(162/346 Pages) MICROCHIP

162 / 346 page

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

DS70318D-page 160

Preliminary

10.4.2.3

Virtual Pins

dsPIC33FJ06GS101/X02

and

dsPIC33FJ16GSX02/X04 devices support four virtual

RPn pins (RP32, RP33, RP34 and RP35), which are

identical in functionality to all other RPn pins, with the

exception of pinouts. These four pins are internal to the

devices and are not connected to a physical device pin.

These pins provide a simple way for inter-peripheral

connection without utilizing a physical pin. For example,

the output of the analog comparator can be connected to

RP32 and the PWM Fault input can be configured for

RP32 as well. This configuration allows the analog

comparator to trigger PWM Faults without the use of an

actual physical pin on the device.

10.4.3

CONTROLLING CONFIGURATION

CHANGES

Because peripheral remapping can be changed during

run time, some restrictions on peripheral remapping

are needed to prevent accidental configuration

changes. dsPIC33F devices include three features to

prevent alterations to the peripheral map:

• Control register lock sequence

• Continuous state monitoring

• Configuration bit pin select lock

10.4.3.1

Control Register Lock

Under normal operation, writes to the RPINRx and

RPORx registers are not allowed. Attempted writes

appear to execute normally, but the contents of the

registers remain unchanged. To change these

registers, they must be unlocked in hardware. The

(OSCCON<6>). Setting IOLOCK prevents writes to the

control registers; clearing IOLOCK allows writes.

To set or clear IOLOCK, a specific command sequence

must be executed:

Write 0x46 to OSCCON<7:0>.

Write 0x57 to OSCCON<7:0>.

Clear (or set) IOLOCK as a single operation.

Unlike the similar sequence with the oscillator’s LOCK

bit, IOLOCK remains in one state until changed. This

allows all of the peripheral pin selects to be configured

with a single unlock sequence followed by an update to

all control registers, then locked with a second lock

sequence.

10.4.3.2

Continuous State Monitoring

In addition to being protected from direct writes, the

contents of the RPINRx and RPORx registers are

constantly monitored in hardware by shadow registers.

If an unexpected change in any of the registers occurs

(such as cell disturbances caused by ESD or other

external events), a Configuration Mismatch Reset will

be triggered.

10.4.3.3

Configuration Bit Pin Select Lock

As an additional level of safety, the device can be

configured to prevent more than one write session to

the RPINRx and RPORx registers. The IOL1WAY

(FOSC<5>) Configuration bit blocks the IOLOCK bit

from being cleared after it has been set once. If

IOLOCK remains set, the register unlock procedure will

not execute and the Peripheral Pin Select Control

registers cannot be written to. The only way to clear the

bit and re-enable peripheral remapping is to perform a

device Reset.

In the default (unprogrammed) state, IOL1WAY is set,

restricting users to one write session. Programming

IOL1WAY allows user applications unlimited access

(with the proper use of the unlock sequence) to the

Peripheral Pin Select registers.

Note:

MPLAB® C30 provides built-in C language

functions for unlocking the OSCCON

__builtin_write_OSCCONL(value)

__builtin_write_OSCCONH(value)

See MPLAB C30 Help files for more

information.

DSPIC33FJ06GS201TE/MM Datasheet(PDF) 162 Page - Microchip Technology

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