IO96NDB2V1 datasheet(27/242 Pages) MICROSEMI

27 / 242 page

ProASIC3L Low Power Flash FPGAs

Revision 13

2-11

Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1

Applicable to Pro I/Os

CLOAD (pF)

VCCI (V)

Static Power

PDC7 (mW)2

Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL/LVCMOS

3.3

–

148.00

2.5 V LVCMOS

2.5

–

83.23

1.8 V LVCMOS

1.8

–

54.58

1.5 V LVCMOS (JESD8-11)

1.5

–

37.05

1.2 V LVCMOS

1.2

–

17.94

3.3 V PCI

3.3

–

204.61

3.3 V PCI-X

3.3

–

204.61

Voltage-Referenced

3.3 V GTL

3.3

–

24.08

2.5 V GTL

2.5

–

13.52

3.3 V GTL+

3.3

–

24.10

2.5 V GTL+

2.5

–

13.54

HSTL (I)

1.5

7.08

26.22

HSTL (II)

1.5

13.88

27.22

SSTL2 (I)

2.5

16.69

105.56

SSTL2 (II)

2.5

25.91

116.60

SSTL3 (I)

3.3

26.02

114.87

SSTL3 (II)

3.3

42.21

131.76

Differential

LVDS

–

2.5

7.70

89.62

LVPECL

–

3.3

19.42

168.02

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

IO96NDB2V1 Datasheet(PDF) 27 Page - Microsemi Corporation

IO96NDB2V1 Datasheet(HTML) 27 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL