IO96NDB2V1 datasheet(46/242 Pages) MICROSEMI

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ProASIC3L DC and Switching Characteristics

2-30

Revision 13

1.2 V DC Core Voltage

Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V,

Worst Case VCCI

Pro I/O Banks

Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA 12 mA High 5

– 0.66 1.89 0.04 1.34 1.85 0.43 1.93 1.42 2.51 2.77 3.64 3.13 ns

3.3 V LVCMOS

Wide Range1,2

100 µA 12 mA High 5

–

–––––

2.5 V LVCMOS 12 mA 12 mA High 5

– 0.66 1.92 0.04 1.58 1.97 0.43 1.96 1.59 2.58 2.68 3.67 3.30 ns

1.8 V LVCMOS 12 mA 12 mA High 5

– 0.66 2.14 0.04 1.53 2.17 0.43 2.18 1.76 2.86 3.24 3.89 3.47 ns

1.5 V LVCMOS 12 mA 12 mA High 5

– 0.66 2.46 0.04 1.69 2.36 0.43 2.51 2.04 3.03 3.35 4.22 3.75 ns

1.2 V LVCMOS 2 mA 2 mA High 5

– 0.66 4.12 0.04 2.02 2.99 0.43 3.83 3.37 4.06 3.84 5.48 5.02 ns

1.2 V LVCMOS

Wide Range1,3

100 µA 2 mA High 5

–

–––––

3.3 V PCI

Per

PCI

spec.

–

High 10 254 0.66 2.15 0.04 2.10 2.84 0.43 2.19 1.53 2.51 2.77 3.90 3.24 ns

3.3 V PCI-X

Per

PCI-X

spec.

–

High 10 254 0.66 2.15 0.04 2.10 2.84 0.43 2.19 1.53 2.51 2.77 3.90 3.24 ns

3.3 V GTL

20 mA6

–

High 10 25 0.66 1.59 0.04 1.80

–

0.43 1.56 1.59

–

3.27 3.30 ns

2.5 V GTL

20 mA6

–

High 10 25 0.66 1.63 0.04 1.75

–

0.43 1.66 1.63

–

3.37 3.34 ns

3.3 V GTL+

35 mA

–

High 10 25 0.66 1.57 0.04 1.80

–

0.43 1.60 1.57

–

3.31 3.29 ns

2.5 V GTL+

33 mA

–

High 10 25 0.66 1.69 0.04 1.75

–

0.43 1.72 1.61

–

3.43 3.32 ns

HSTL (I)

8 mA

–

High 20 25 0.66 2.43 0.04 2.12

–

0.43 2.48 2.41

–

4.19 4.12 ns

HSTL (II)

15 mA6

–

High 20 50 0.66 2.32 0.04 2.12

–

0.43 2.36 2.08

–

4.07 3.79 ns

SSTL2 (I)

15 mA

–

High 30 25 0.66 1.63 0.04 1.61

–

0.43 1.66 1.41

–

1.66 1.41 ns

SSTL2 (II)

18 mA

–

High 30 50 0.66 1.66 0.04 1.61

–

0.43 1.69 1.36

–

1.69 1.36 ns

SSTL3 (I)

14 mA

–

High 30 25 0.66 1.77 0.04 1.54

–

0.43 1.80 1.41

–

1.80 1.41 ns

SSTL3 (II)

21 mA

–

High 30 50 0.66 1.58 0.04 1.54

–

0.43 1.61 1.28

–

1.61 1.28 ns

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for

connectivity. This resistor is not required during normal operation.

5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

6. Output drive strength is below JEDEC specification.

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