AS3515_08 datasheet(23/67 Pages) AMSCO

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AS3515 V15

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 3.1

- 66

6.6.6

Parameter

Table 20 DAC/ADC Block Parameter

Symbol Parameter

Notes

Min

Typ

Max

Unit

programmable gain DAC input

-43.43

1.07

Gain

programmable gain ADC output

-34.5

Gain Step-Size

1.5

Gain Step-Precision

0.5

Mute Attenuation

100

I2S inputs / outputs

VIL

SCLK, LRCK, SDI (30%DVDD/2)

0.42

VIH

SCLK, LRCK, SDI (70%DVDD/2)

1.02

DVDD

VOL

SDO @ 2mA

0.3

VOH

SDO @ 2mA

2.6

tsu

Set-up Time

SDI versus high going edge of SCLK

thd

Hold Time

SDI versus high going edge of SCLK

ts1, ts2

Separation Time

SCLK high going edges separation from

LRCK edges

tjitter

clock Jitter

LRCK

-20

BVDD = 3.3V, DVDD = 2.9V, TA= 25oC unless otherwise mentioned

6.6.7

Enabling the DAC or ADC is done via a control bit in the audio settings register (AudioSet1 register 0x14h). To get an interrupt on a LRCK

state change, the corresponding bit in the IRQ_ENRD1 register (0x25h) has to be set. Changing the bias current and adding a dither

signal is done via AudioSet2 register (0x15h). All other DAC or ADC settings are controlled by the following two registers.

Right DAC Register (0Eh)

Table 21 DAC_R Register

Bit

Name

Description

7..5

4..0

DAR_VOL

volume settings for right DAC input, adjustable in 32 steps @ 1.5dB

11111: 6 dB gain

11110: 4.5 dB gain

00001: -39 dB gain

00000: -40.5 dB gain

The register is R/W; default value is 00h

Left DAC Register (0Fh)

Table 22 DAC_R Register

Bit

Name

Description

DAC_Mute_off 0: DAC input is set to mute

1: normal operation

4..0

DAL_VOL

volume settings for left DAC input, adjustable in 32 steps @ 1.5dB

11111: 6 dB gain

11110: 4.5 dB gain

00001: -39 dB gain

00000: -40.5 dB gain

The register is R/W; default value is 00h

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