T89C51RD2-3CWC-M datasheet(37/86 Pages) ATMEL

37 / 86 page

Rev. F - 15 February, 2001

T89C51RD2

6.7. Interrupt System

The T89C51RD2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts

(timers 0, 1 and 2), the serial port interrupt and the PCA global interrupt. These interrupts are shown in Figure 16.

Figure 16. Interrupt Control System

Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt

Enable register (See Table 18.). This register also contains a global disable bit, which must be cleared to disable

all interrupts at once.

Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing

a bit in the Interrupt Priority register (See Table 19.) and in the Interrupt Priority High register (See Table 20.).

shows the bit values and priority levels associated with each combination.

The PCA interrupt vector is located at address 0033H. All other vectors addresses are the same as standard C52

devices.

IE1

High priority

interrupt

Interrupt

polling

sequence, decreasing

from high to low priority

Low priority

interrupt

Global Disable

Individual Enable

EXF2

TF2

TF0

INT0

INT1

TF1

IPH, IP

IE0

PCA IT

T89C51RD2-3CWC-M Datasheet(PDF) 37 Page - ATMEL Corporation