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T89C51RD2-3CWC-M Datasheet(PDF) 39 Page - ATMEL Corporation |
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T89C51RD2-3CWC-M Datasheet(HTML) 39 Page - ATMEL Corporation |
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39 / 86 page  Rev. F - 15 February, 2001 39 T89C51RD2 Table 19. IP Register IP - Interrupt Priority Register (B8h) Reset Value = X000 0000b Bit addressable 7 6 5 4 3 2 1 0 - PPC PT2 PS PT1 PX1 PT0 PX0 Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 PPC PCA interrupt priority bit Refer to PPCH for priority level. 5 PT2 Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level. 4 PS Serial port Priority bit Refer to PSH for priority level. 3 PT1 Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. 2 PX1 External interrupt 1 Priority bit Refer to PX1H for priority level. 1 PT0 Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. 0 PX0 External interrupt 0 Priority bit Refer to PX0H for priority level. |
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