AFE032 datasheet(27/77 Pages) TI1

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DIN

SCLK

DOUT

SPI

Slave

ASYNCH

FIFO

Device Control

SCLK

Valid

Data

Write Data

Address

Read Data

Clock Divider

XCLK

Block 1

Bypass

Block 2

Bypass

Block 3

Bypass

Block 4

Bypass

Clip and

Offset

12-Bit

DAC

DAC_CLK

DAC_OUT

Device DSP Path

AFE032

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SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013

A minimum of ten DAC_CLK cycles must be inserted between consecutive write operations and a minimum of

five DAC_CLK cycles must be inserted between consecutive read operations.

DAC Mode

The device digital logic contains four digital processing blocks to condition incoming DAC samples delivered from

an external processor. The digital processing blocks in the device are referred to as the DSP path, as shown in

Figure 22.

Figure 22. AFE032 DSP Path

Each block in the DSP path can be enabled or disabled to accommodate for different application scenarios.

Processing DAC samples through the device can be broken down as follows:

•

The device receives DAC samples (12 bits per sample) from an external DSP through the SPI at a rate of fS

samples per second.

•

The device receives the 12-bit samples and processes them as real signed numbers. Thus, bit 11 is

processed as a sign bit. Therefore, the absolute value of each sample has 11 bits of resolution.

•

The device extracts the DAC samples from the SPI and synchronizes them to DAC_CLK through the

ASYNCH FIFO.

NOTE

The only exception to the 12-bit DAC sample length is when using a 16-bit envelope. See

the SPI Envelope Exception Case section for more details.

When an external DSP is ready to send DAC samples to the device, the DAC_MODE pin is asserted. The device

digital logic reconfigures the SPI slave to run in a proprietary mode of operation in order to receive samples from

the external DSP. In other words, the SPI interface becomes a write-only serial interface so that the external

DSP can send DAC samples to the device. Each sample must be 12 bits wide.

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