AFE032 datasheet(31/77 Pages) TI1

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AFE032

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SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013

Refer to Figure 22 for the block diagram of the AFE032 DSP path. Bits 1 though 4 of the REG_AFE032_CTRL

these bits is '0' and all four blocks are included in the DSP path when the device is powered up.

Block 3 of the DSP path operates synchronously with DAC_CLK and interpolates (by a factor of four) the signals

coming from the ASYNCH FIFO. Such interpolation requires that samples stored in the ASYNCH FIFO be

extracted no faster than one time every four DAC_CLK cycles; such interpolation also imposes an upper bound

to fS. The external DSP must send samples to the device at a rate less than or equal to one-fourth the DAC_CLK

frequency [that is, fS ≤ (DAC_CLK / 4)].

Block 4 should be used to improve performance in two cases:

•

When block 3 is included in the DSP path and fS is strictly less than one-fourth the DAC_CLK frequency [that

is, fS < (DAC_CLK / 4)].

•

When block 3 is bypassed (not included in the DSP path) and fS is strictly less than the DAC_CLK frequency

(that is, fS < DAC_CLK).

For these two cases, block 4 should be used and its 32-bit parameter should be written to the REG_OFFSET0,

REG_OFFSET1, REG_OFFSET2, and REG_OFFSET3 registers. This section describes four typical scenarios

that can be found in most applications.

Block 3 and Block 4 Are Bypassed

If an external DSP transmits DAC samples to the device at a rate equal to the DAC_CLK frequency (that is, fS =

DAC_CLK), then both block 3 and block 4 should be bypassed. Write a '0' to bits 1 to 4 of the

REG_AFE032_CTRL register. A parameter for block 4 does not need to be calculated or written. Table 9 shows

examples of this scenario.

Table 9. Example Cases of Bypassed Blocks 3 and 4

XCLK

DAC_CLK

(kSPS)

(MHz)

DIVIDER

REG_CLK_DIV (Hex)

(MHz)

BLOCK 3

BLOCK 4

500

37.5

0.5

Bypassed

800

19.2

0.8

Bypassed

Block 3 Is Included, Block 4 Is Bypassed

If an external DSP transmits DAC samples to the device at a rate equal to one-fourth the DAC_CLK frequency

[that is, fS = (DAC_CLK / 4)], then block 3 is included and block 4 is bypassed. Write a '0' to bits 1, 2, and 4 and

write a '1' to bit 3 of the REG_AFE032_CTRL register. A parameter for block 4 does not need to be calculated or

written. Table 10 shows examples of this scenario.

Table 10. Example Cases of Block 3 Included and Block 4 Bypassed

XCLK

DAC_CLK

(MSPS)

(MHz)

DIVIDER

REG_CLK_DIV (Hex)

(MHz)

BLOCK 3

BLOCK 4

1.2

19.2

4.8

Included

Bypassed

0.625

37.5

2.5

Included

Bypassed

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