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AFE032 Datasheet(PDF) 10 Page - Texas Instruments |
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AFE032 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 77 page  AFE032 SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013 www.ti.com SPI TIMING REQUIREMENTS PARAMETER MIN TYP MAX UNIT Input capacitance 1 pF tRFI Input rising and falling time (CS, DIN, SCLK) 2 ns tRFO DOUT rising and falling time 10 ns DAC_CLK tCSH CS high time 10 cycles(1) tCS0 SCLK edge to CS falling edge setup time 10 ns tCSSC CS falling edge to first SCLK edge setup time 10 ns fSCLK SCLK frequency 20 30 MHz tHI SCLK high time 16.7 25 ns tLO SCLK low time 16.7 25 ns tSCCS SCLK last edge to CS rising edge setup time 10 ns tCS1 CS rising edge to SCLK edge setup time 10 ns tSU DIN setup time 5 ns tHD DIN hold time 5 ns tDO SCLK to DOUT valid propagation delay 16 ns tsoz CS rising edge to DOUT forced to Hi-Z 20 ns (1) CS pin must remain high for at least ten DAC_CLK cycles after a write operation and must remain high for at least five DAC_CLK cycles after a read operation. 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AFE032 |
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