R5F110MF datasheet(32/153 Pages) RENESAS

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RL78/L1C

2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 °C)

R01DS0192EJ0200 Rev. 2.00

Page 32 of 149

Feb 21, 2014

Note 1.

Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD, or

VSS. The values below the MAX. column include the peripheral operation current. However, not including the current

flowing into the LCD controller/driver, A/D converter, D/A converter, comparator, LVD circuit, USB 2.0 function module,

I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.

Note 2.

When high-speed on-chip oscillator and subsystem clock are stopped.

Note 3.

When high-speed system clock and subsystem clock are stopped.

Note 4.

When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power

consumption oscillation). However, not including the current flowing into the real-time clock 2, 12-bit interval timer, and

watchdog timer.

Note 5.

Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.

HS (high-speed main) mode:

2.7 V

 VDD  3.6 V@1 MHz to 24 MHz

2.4 V

 VDD  3.6 V@1 MHz to 16 MHz

LS (low-speed main) mode:

1.8 V

 VDD  3.6 V@1 MHz to 8 MHz

LV (low-voltage main) mode

1.6 V

 VDD  3.6 V@1 MHz to 4 MHz

Remark 1.

fMX:

High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)

Remark 2.

fHOCO: High-speed on-chip oscillator clock frequency (48 MHz max.)

Remark 3.

fIH:

Main system clock source frequency when the high-speed on-chip oscillator clock divided 1, 2, 4, or 8, or the PLL

clock divided by 2, 4, or 8 is selected (24 MHz max.)

Remark 4.

fSUB:

Subsystem clock frequency (XT1 clock oscillation frequency)

Remark 5.

Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C

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