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CS43L42 Datasheet(PDF) 10 Page - Cirrus Logic |
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CS43L42 Datasheet(HTML) 10 Page - Cirrus Logic |
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10 / 40 page ![]() CS43L42 10 DS481PP2 SWITCHING CHARACTERISTICS (T A = -10 to 70° C; VL = 1.7 V - 3.6 V; Inputs: Logic 0 = GND, Logic 1 = VL, CL =20pF) Notes: 11. Internal SCLK Mode timing is not tested, but is guaranteed by design. 12. In Internal SCLK Mode, the LRCK duty cycle must be 50% +/− 1/2 MCLK Period. Parameters Symbol Min Typ Max Units Input Sample Rate Base Rate Mode High Rate Mode Fs Fs 2 50 - - 50 100 kHz kHz MCLK Pulse Width High MCLK/LRCK = 1024 7 - - ns MCLK Pulse Width Low MCLK/LRCK = 1024 7 - - ns MCLK Pulse Width High MCLK/LRCK = 768 10 - - ns MCLK Pulse Width Low MCLK/LRCK = 768 10 - - ns MCLK Pulse Width High MCLK/LRCK = 512 15 - - ns MCLK Pulse Width Low MCLK/LRCK = 512 15 - - ns MCLK Pulse Width High MCLK / LRCK = 384 or 192 25 - - ns MCLK Pulse Width Low MCLK / LRCK = 384 or 192 25 - - ns MCLK Pulse Width High MCLK / LRCK = 256 or 128 35 - - ns MCLK Pulse Width Low MCLK / LRCK = 256 or 128 35 - - ns External SCLK Mode LRCK Duty Cycle (External SCLK only) 40 50 60 % SCLK Pulse Width Low tsclkl 20 - - ns SCLK Pulse Width High tsclkh 20 - - ns SCLK Period Base Rate Mode tsclkw -- ns High Rate Mode tsclkw -- ns SCLK rising to LRCK edge delay tslrd 20 - - ns SCLK rising to LRCK edge setup time tslrs 20 - - ns SDATA valid to SCLK rising setup time tsdlrs 20 - - ns SCLK rising to SDATA hold time tsdh 20 - - ns Internal SCLK Mode (Note 11) LRCK Duty Cycle (Internal SCLK only) (Note 12) - 50 - % SCLK Period tsclkw -- ns SCLK rising to LRCK edge tsclkr -- µs SDATA valid to SCLK rising setup time tsdlrs -- ns SCLK rising to SDATA hold time Base Rate Mode tsdh -- ns High Rate Mode tsdh -- ns 1 128 ()Fs ---------------------- 1 64 ()Fs ------------------- 1 SCLK ----------------- tsclkw 2 ------------------ 1 512 ()Fs ----------------------10 + 1 512 ()Fs ----------------------15 + 1 384 ()Fs ----------------------15 + |
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