CS43L42 datasheet(36/40 Pages) CIRRUS

36 / 40 page

CS43L42

DS481PP2

Figure 25. CS43L42 Control Port Mode - Serial Audio Format 6

LR C K

SCL K

Left C hann e l

R ight C h an nel

SD A T A

321

15 14 13 12 11 10

321

15 14 13 12 11 10

17 16

32 clocks

Internal SCLK Mode

External SCLK Mode

Right Justified, 18-Bit Data

INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128

INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

Right Justified, 18-Bit Data

Data Valid on Rising Edge of SCLK

SCLK Must Have at Least 36 Cycles per LRCK Period

LR C K

SC L K

Le ft C ha n nel

Rig h t Cha n nel

SD A T A

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4 -5

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4

Internal SCLK Mode

External SCLK Mode

I2S, Up to 24-Bit data and INT SCLK = 64 Fs if

MCLK/LRCK = 512, 256 or 128

I2S, Up to 24-Bit data and INT SCLK = 48 Fs if

MCLK/LRCK = 384 or 192

I2S, up to 24-Bit Data

Data Valid on Rising Edge of SCLK

Figure 26. CS43L42 Stand Alone Mode - Serial Audio Format 0

Figure 27. CS43L42 Stand Alone Mode - Serial Audio Format 1

LR C K

SC L K

Left C h a n n e l

R igh t C h ann e l

SD A T A

+3 +2 +1 LS B

+5 +4

MSB -1 -2 -3 -4 -5

+3 +2 +1 LS B

+5 +4

MS B -1 -2 -3 -4

Internal SCLK Mode

External SCLK Mode

Left Justified, up to 24-Bit Data

INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128

INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

Left Justified, up to 24-Bit Data

Data Valid on Rising Edge of SCLK

CS43L42 Datasheet(PDF) 36 Page - Cirrus Logic

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