CS43L42 datasheet(30/40 Pages) CIRRUS

30 / 40 page

CS43L42

DS481PP2

To prevent an audio transient at the next power-on,

the DC-blocking capacitors must fully discharge

before turning off the power or exiting the pow-

er-down state. If full discharge does not occur, a

transient will occur when the audio outputs are ini-

tially clamped to GND. The time that the device

must remain in the power-down state is related to

the value of the DC-blocking capacitance and the

output load. For example, with a 220 µF capacitor

and a 16 ohm load on the headphone outputs, the

minimum power-down time will be approximately

0.4 seconds.

Use of the Mute Control function on the line out-

puts is recommended for designs requiring the ab-

solute minimum in extraneous clicks and pops.

Also, use of the Mute Control function can enable

the system designer to achieve idle channel

noise/signal-to-noise ratios only limited by the ex-

ternal mute circuit. See the CDB43L42 Datasheet

for a suggested mute circuit.

7. CONTROL PORT INTERFACE

The control port is used to load all the internal set-

tings. The operation of the control port may be

completely asynchronous with the audio sample

rate. However, to avoid potential interference prob-

lems, the control port pins should remain static if

no operation is required.

The control port has 2 modes: SPI and Two-Wire,

with the CS43L42 operating as a slave device. If

Two-Wire operation is desired, AD0/CS should be

tied to VL or GND. If the CS43L42 ever detects a

high to low transition on AD0/CS after power-up,

SPI mode will be selected.

7.1 SPI Mode

In SPI mode, CS is the CS43L42 chip select signal,

CCLK is the control port bit clock, CDIN is the in-

put data line from the microcontroller and the chip

address is 0010000. All signals are inputs and data

is clocked in on the rising edge of CCLK. Figure 7

shows the operation of the control port in SPI

mode. To write to a register, bring CS low. The first

7 bits on CDIN form the chip address and must be

0010000. The eighth bit is a read/write indicator

(R/W), which must be low to write. The next 8 bits

form the Memory Address Pointer (MAP), which is

set to the address of the register that is to be updat-

ed. The next 8 bits are the data which will be placed

into register designated by the MAP.

The CS43L42 has a MAP auto increment capabili-

ty, enabled by the INCR bit in the MAP register. If

INCR is a zero, then the MAP will stay constant for

successive writes. If INCR is set to a 1, then MAP

will auto increment after each byte is written, al-

lowing block writes of successive registers.

7.2 Two-Wire Mode

In Two-Wire mode, SDA is a bidirectional data

line. Data is clocked into and out of the part by the

clock, SCL, with the clock to data relationship as

shown in Figure 8. There is no CS pin. Pin AD0

forms the partial chip address and should be tied to

VL or GND as required. The upper 6 bits of the 7

bit address field must be 001000. To communicate

with the CS43L42, the LSB of the chip address

field, which is the first byte sent to the CS43L42,

should match the setting of the AD0 pin. The eighth

bit of the address byte is the R/W bit (high for a

read, low for a write). If the operation is a write, the

next byte is the Memory Address Pointer, MAP,

which selects the register to be read or written. The

MAP is then followed by the data to be written. If

the operation is a read, the contents of the register

pointed to by the MAP will be output after the chip

address.

The CS43L42 has MAP auto increment capability,

enabled by the INCR bit in the MAP register. If

INCR is 0, then the MAP will stay constant for suc-

cessive writes. If INCR is set to 1, then MAP will

auto increment after each byte is written, allowing

block reads or writes of successive registers.

The Two-Wire mode is compatible with the I2C

protocol.

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