CS5101A datasheet(12/40 Pages) CIRRUS

12 / 40 page

GENERAL DESCRIPTION

The CS5101A and CS5102A are 2-channel, 16-

bit A/D converters. The devices include an

inherent sample/hold and an on-chip analog

switch for 2-channel operation. Both channels

can thus be sampled and converted at rates up to

50 k Hz each (CS5101A) or 10 kHz each

(CS5102A). Alternatively, each of the devices

can be operated as a single channel ADC operat-

ing at 100 kHz (CS5101A) or 20 kHz

(CS5102A).

Both the CS5101A and CS5102A can be config-

ured to accept either unipolar or bipolar input

ranges, and data is output serially in either binary

or 2’s complement coding. The devices can be

configured in 3 different output modes, as well as

an internal, synchronous loopback mode. The

CS5101A and CS5102A prov ide co arse

charge/fine charge control, to allow accurate

tracking of high-slew signals.

THEORY OF OPERATION

The CS5101A and CS5102A implement the suc-

cessive approximation algorithm using a charge

redistribution architecture. Instead of the tradi-

tional resistor network, the DAC is an array of

binary-weighted capacitors. All capacitors in the

array share a common node at the comparator’s

input. As shown in Figure 1, their other terminals

are capable of being connected to AGND, VREF,

or AIN (1 or 2). When the device is not calibrat-

ing or converting, all capacitors are tied to AIN.

Switch S1 is closed and the charge on the array,

tracks the input signal.

When the conversion command is issued, switch

S1 opens. This traps the charge on the compara-

tor side of the capacitor array and creates a

floating node at the comparator’s input. The con-

version algorithm operates on this fixed charge,

and the signal at the analog input pin is ignored.

In effect, the entire DAC capacitor array serves

as analog memory during conversion much like a

hold capacitor in a sample/hold amplifier.

The conversion consists of manipulating the free

plates of the capacitor array to VREF and AGND

to form a capacitive divider. Since the charge at

the floating node remains fixed, the voltage at

that point depends on the proportion of capaci-

tance ti ed to VREF versus AGND. Th e

successive-approximation algorithm is used to

find the proportion of capacitance, which when

connected to the reference will drive the voltage

at the floating node to zero. That binary fraction

of capacitance represents the converter’s digital

output.

AIN

C/2

C/32,768

MSB

LSB

Bit 15

Bit 14

Bit 13

Bit 0

= C + C/2 + C/4 + C/8 + ... C/32,768

tot

Dummy

C/32,768

C/4

Fine

VREF

AGND

Coarse

Fine

Coarse

Fine

Figure 1. Coarse Charge Input Buffers and Charge Redistribution DAC

CS5101A CS5102A

DS45F2

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