CS5101A datasheet(18/40 Pages) CIRRUS

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Registered Burst Transmission (RBT)

RBT mode is selected by tying SCKMOD high,

and OUTMOD low. As in PDT mode, SCLK is

an input, however data is available immediately

following conversion, and may be clocked out

the moment TRK1 or TRK2 falls. The falling

edge of HOLD clears the output buffer, so any

unread data will be lost. A new conversion may

be initiated before all the data has been clocked

out if the unread data bits are not important

(Figure 4).

Synchronous Self-Clocking (SSC)

SSC mode is selected by tying SCKMOD low,

and OUTMOD high. In SSC mode, SCLK is an

output, and will clock out each bit of the data as

it’s being converted. SCLK will remain high be-

tween conversions, and run at a rate of 1/4 the

master clock speed for 16 low pulses during con-

version (Figure 5).

The SSH/SDL goes low coincident with the first

falling edge of SCLK, and returns high 2 CLKIN

cycles after the last rising edge of SCLK. This

signal frames the 16 data bits and is useful for

interfacing to shift registers (e.g. 74HC595) or to

DSP serial ports.

Free Run (FRN)

Free Run is the internal, synchronous loopback

mode. FRN mode is selected by tying SCKMOD

and OUTMOD low. SCLK is an output, and op-

erates exactly the same as in the SSC mode. In

Free Run mode, the converter initiates a new

conversion every 80 master clock cycles, and al-

ternates between channel 1 and channel 2. HOLD

is disabled, and should be tied to either VD+ or

DGND. CH1/2 is an output, and will change at

the start of each new conversion cycle, indicating

which channel will be tracked after the current

conversion is finished (Figure 6).

The SSH/SDL goes low coincident with the first

falling edge of SCLK, and returns high 2 CLKIN

cycles after the last rising edge of SCLK. This

signal frames the 16 data bits and is useful for

interfacing to shift registers (e.g. 74HC595) or to

DSP serial ports.

SYSTEM DESIGN WITH THE CS5101A

AND CS5102A

Figure 7 shows a general system connection dia-

gram for the CS5101A and CS5102A.

Digital Circuit Connections

When TTL loads are utilized the potential for

crosstalk between digital and analog sections of

the system is increased. This crosstalk is due to

high digital supply and signal currents arising

from the TTL drive current required of each digi-

tal output. Connecting CMOS logic to the digital

outputs is recommended. Suitable logic families

include 4000B, 74HC, 74AC, 74ACT, and

74HCT.

System Initialization

Upon power up, the CS5101A and CS5102A

must be reset to guarantee a consistent starting

condition and initially calibrate the device. Due

to each device’s low power dissipation and low

temperature drift, no warm-up time is required

before reset to accommodate any self-heating ef-

fects. However, the voltage reference input

should have stabilized to within 0.25% of its final

value before RST rises to guarantee an accurate

calibration. Later, the CS5101A and CS5102A

may be reset at any time to initiate a single full

calibration.

When RST is brought low all internal logic

clears. When RST returns high on the CS5101A,

a calibration cycle begins which takes 11,528,160

master clock cycles to complete (approximately

1.4 seconds with an 8 MHz master clock). The

CS5101A CS5102A

DS45F2

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