OPA690IDBVT datasheet(23/37 Pages) TI1

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E =

2 +(I R ) +4kTR

NG +(I R ) +4kTR NG

E =

I R

+(I

R ) +4kTR +

4kTR

1kW

±200mVOutputAdjustment

= 2

Power-supplydecoupling

notshown.

5kW

328W

0.1 F

500W

20kW

10kW

0.1 F

-5V

+5V

OPA690

+5V

-5V

OPA690

www.ti.com

SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010

The total output spot noise voltage can be computed

–(NG = noninverting signal gain)

as the square root of the sum of all squared output

±(NG × VOS(MAX)) ± (RF × IOS(MAX))

noise voltage contributors. Equation 3 shows the

= ±(2 × 4mV) ± (402

Ω × 1mA)

general form for the output noise voltage using the

= ±8.4mV

terms shown in Figure 46.

A fine-scale output offset null, or dc operating point

adjustment, is often required. Numerous techniques

are available for introducing dc offset control into an

(3)

op amp circuit. Most of these techniques eventually

Dividing this expression by the noise gain [NG = (1 +

reduce to adding a dc current through the feedback

RF/RG)] will give the equivalent input-referred spot

resistor. In selecting an offset trim method, one key

noise voltage at the noninverting input, as shown in

consideration is the impact on the desired signal path

Equation 4.

frequency response. If the signal path is intended to

be noninverting, the offset control is best applied as

an inverting summing signal to avoid interaction with

the signal source. If the signal path is intended to be

(4)

inverting,

applying

the

offset

control

the

noninverting input may be considered. However, the

Evaluating these two equations for the OPA690

dc offset voltage on the summing junction will set up

circuit and component values (see Figure 36) gives a

a dc current back into the source that must be

total output spot noise voltage of 12.3nV/

√Hz and a

considered. Applying an offset adjustment to the

total equivalent input spot noise voltage of 6.1nV/

√Hz.

inverting op amp input can change the noise gain and

This is including the noise added by the bias current

frequency

response

flatness.

For

dc-coupled

cancellation resistor (175

Ω) on the noninverting input.

inverting amplifier, see Figure 47 for one example of

This total input-referred spot noise voltage is only

an offset adjustment technique that has minimal

slightly higher than the 5.5nV/

√Hz specification for the

impact on the signal frequency response. In this

op amp voltage noise alone. This will be the case as

case, the dc offsetting current is brought into the

long as the impedances appearing at each op amp

inverting input node through resistor values that are

input are limited to the previously recommend

much larger than the signal path resistors. This

maximum value of 300

Ω. Keeping both (RF || RG) and

ensures that the adjustment circuit has minimal effect

the noninverting input source impedance less than

on the loop gain and hence, the frequency response.

300

Ω will satisfy both noise and frequency response

flatness considerations. Since the resistor-induced

noise is relatively negligible, additional capacitive

decoupling across the bias current cancellation

resistor (RB) for the inverting op amp configuration of

Figure 43 is not required.

DC ACCURACY AND OFFSET CONTROL

The

balanced

input

stage

wideband

voltage-feedback op amp allows good output dc

accuracy in a wide variety of applications. The

power-supply current trim for the OPA690 gives even

tighter control than comparable amplifiers. Although

the high-speed input stage does require relatively

high input bias current (typically ±8µA at each input

terminal), the close matching between them may be

used to reduce the output dc error caused by this

current. The total output offset voltage may be

considerably reduced by matching the dc source

resistances appearing at the two inputs. This reduces

the output dc error due to the input bias currents to

Figure 47. DC-Coupled, Inverting Gain of -2, with

the

offset

current

times

the

feedback

resistor.

Offset Adjustment

Evaluating the configuration of Figure 36, and using

worst-case +25°C input offset voltage and current

specifications,

gives

worst-case

output

offset

voltage equal to:

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