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HM17CM256 Datasheet(PDF) 101 Page - Hynix Semiconductor |
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HM17CM256 Datasheet(HTML) 101 Page - Hynix Semiconductor |
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101 / 111 page  HM17CM256 - 101 - • SERIAL INTERFACE TIMING (VDD=2.7 ∼3.3V, Ta=-30∼+85°C) ITEM SYMBOL CONDITION MIN. MAX. UNIT PORT Serial clock cycle SCL ”H” pulse width SCL ”L” pulse width tCYCS tSHW tSLW TBD TBD TBD ns ns ns SCL Address setup timing Address hold timing tASS tAHS TBD TBD ns ns RS Data setup timing Data hold timing tDSS tDHS TBD TBD ns ns SDA CS – SCL timing CS hold timing tCSS tCSH TBD TBD ns ns (VDD=2.4 ∼2.7V, Ta=-30∼+85°C) ITEM SYMBOL CONDITION MIN. MAX. UNIT PORT Serial clock cycle SCL ”H” pulse width SCL ”L” pulse width tCYCS tSHW tSLW TBD TBD TBD ns ns ns SCL Address setup timing Address hold timing tASS tAHS TBD TBD ns ns RS Data setup timing Data hold timing tDSS tDHS TBD TBD ns ns SDA CS – SCL timing CS hold timing tCSS tCSH TBD TBD ns ns notice) All timing reference is 20% and 80% of VDD and 80%. CS tCSS CS RS tCSH SDA tSLW tSHW tDSS tDHS tCYCS SCL tAHS tASS CS |
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