HM17CM256 datasheet(57/111 Pages) HYNIX

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HM17CM256

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(34-8) Display control (2) register set

RE2

RE1

RE0

REV

NLIN

SWAP

REF

( reset :{REV, NLIN, SWAP, REF}=0H, read address :9H )

various control setting of display

a) REF command

When CPU tries to access display RAM, the relation between X address and write data is changed by

command, normal or headfirst.

The output sequence of display data to segment driver can be controlled by register setting. The IC can

be placed in panel with less constraint at application.

b) SWAP command

When CPU tries to access display RAM, the display data can be swapped.

SWAP=”0”: Normal state, D7~D0 or D15~D0 are written to the RAM.

SWAP=”1”: SWAP mode on : The swapped data of D7~D0 or D15~D0 are written to the RAM.

SWAP=”0”

SWAP=”1”

Write data

D7 D6 D5 D4 D3 D2 D1 D0

Internal data

d7 d6 d5 d4 d3 d2 d1 d0

d0 d1 d2 d3 d4 d5 d6 d7

Read data

D7 D6 D5 D4 D3 D2 D1 D0

c) NLIN command

n line inversion ON/OFF control.

NLIN=”0”: n line inversion OFF. Polarity signal, FR is inverted every other frame.

NLIN=”1”: n line inversion ON. The n lines are inverted according to the contents of n line inversion

d) REV command

The relation between RAM data and display data is defined by this command.

REV=”0”: The display data are reflected the RAM data until that time.

REV=”1”: The display data are reflected the opposite data from RAM data.

HM17CM256 Datasheet(PDF) 57 Page - Hynix Semiconductor