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HM17CM256 Datasheet(PDF) 98 Page - Hynix Semiconductor |
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HM17CM256 Datasheet(HTML) 98 Page - Hynix Semiconductor |
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98 / 111 page ![]() HM17CM256 - 98 - read timing (VDD=2.7 ∼3.3V, Ta=-30∼+85°C) ITEM SYMBOL CONDITION MIN. MAX. UNIT PORT Address hold timing Address setup timing tAH8 tAS8 TBD TBD ns ns CS RS System cycle timing Write ”L” pulse width Write ”H” pulse width tCYC8 tWRLR8 tWRHR8 TBD TBD TBD ns ns ns RD Data setup timing Data hold timing tDS8 tDH8 TBD TBD ns ns D0 ∼ D 15 (VDD=2.4 ∼2.7V, Ta=-30∼+85°C) ITEM SYMBOL CONDITION MIN. MAX. UNIT PORT Address hold timing Address setup timing tAH8 tAS8 TBD TBD ns ns CS RS System cycle timing Write ”L” pulse width Write ”H” pulse width tCYC8 tWRLR8 tWRHR8 TBD TBD TBD ns ns ns RD Data setup timing Data hold timing tDS8 tDH8 TBD TBD ns ns D0 ∼ D 15 (VDD=1.7 ∼2.4V, Ta=-30∼+85°C) ITEM SYMBOL CONDITION MIN. MAX. UNIT PORT Address hold timing Address setup timing tAH8 tAS8 TBD TBD ns ns CS RS System cycle timing Write ”L” pulse width Write ”H” pulse width tCYC8 tWRLR8 tWRHR8 TBD TBD TBD ns ns ns RD Data setup timing Data hold timing tDS8 tDH8 TBD TBD ns ns D0 ∼ D 15 notice) All timing reference is 20% and 80% of VDD and 80%. tAS8 CS RS D0 ∼ D 15 tRDD8 tRDH8 tCYC8 RD tWRLR8 tWRHR8 tAH8 |
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