HM17CM256 datasheet(12/111 Pages) HYNIX

12 / 111 page

HM17CM256

- 12 -

s PIN DESCRIPTION 3

No.

NAME

I/O

FUNCTION

CPU interface selection port

SEL68

status

68 series

80 series

SEL68

Serial / parallel interface selection port

P/S

chip

select

data/

command

data

read/

write

serial clock

D0~D7

RD, WR

SDA(D1)

write only

SCL (D0)

P/S

P/S = “L” :serial interface selection ,D15~D5 goes to Hi-Z

state.

Fix RD, WR to “H” or “L”.

TEST

Test port.

Fix to ”L”.

Latching signal pin of display data.

Display line counter is counted up at the rising edge and LCD

driving signal is generated at the falling edge

M/S

status

master

output

slave

input

I/O

LCD synchronous signal (first line marker) I/O pin.

Display start address is loaded in the display line counter at

FLM = “H”.

M/S

status

FLM

master

output

slave

input

FLM

I/O

Alternated display signal of LCD driver output I/O pin.

M/S

status

master

output

slave

input

I/O

Master / slave mode selection pin

M/S

mode

oscillator

Power supply

master

enable

slave

disable

M/S

Fix to “H” or “L” according to operating mode.

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