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HMS91C8032 Datasheet(PDF) 97 Page - Hynix Semiconductor |
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HMS91C8032 Datasheet(HTML) 97 Page - Hynix Semiconductor |
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97 / 157 page ![]() HMS91C8032/97C8032 94 NOV., 2001 Ver 1.02 RESET TIMING WAVEFORM TIMER INPUT TIMING WAVEFORM SERIAL INTERFACE(SIO) (TA = -40° to +85°, VDD = 3.5 to 5.5 V) • 3-wire serial I/O mode (SCK0 … internal clock output) * Note 1. When fx is 7.2 MHz 2. C is the load capacitance of SO0 output line. 3-wire serial I/O mode (SCK0 … external clock input)* Note 1. When fx is 7.2MHz. * Note 1. When fx is 7.2 MHz 2. C is the load capacitance of SO0 output line. Parameter Symbol Variable MIN. TYP. MAX. Unit SCK0 cycle time TKCY1 Minimum : (1/fx)*2*8 2220Note1 ns SCK0 high/low-level width TKH1 / TKL1 Minimum : TKCY1/2-100 1010Note1 ns SIO setup time (to SCK0 ) TSIK1 300 ns SIO hold time (to SCK0 ) TKSI1 400 ns SO0 output delay time from SCK0 TKSO1 C = 100 pF Note2 300 ns Parameter Symbol Variable MIN. TYP. MAX. Unit SCK0 cycle time TKCY2 Minimum : (1/fx)*2*8 2200Note1 ns SCK0 high/low-level width TKH2 / TKL1 Minimum : TKCY2/2-100 1010Note1 ns SIO setup time (to SCK0 ) TSIK2 100 ns SIO hold time (to SCK0 ) TKSI2 400 ns SO0 output delay time from SCK0 TKSO2 C = 100 pF Note2 300 ns SCK0 at rising or falling edge time TR2 , TF2 100 ns TRSL RESET TTL T0 to T4 1/fTM TTH |
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