HMS91C8032 datasheet(52/157 Pages) HYNIX

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HMS91C8032/97C8032

NOV., 2001 Ver 1.02

4.5 Standard Serial Interface (UART)

The serial port is full duplex, meaning it can transmit and receive

simultaneously. It is also receive-buffered, meaning it can com-

mence reception of a second byte before a previously received

byte has been read from the register. (However, if the first byte

still hasn't been read by the time reception of the second byte is

complete, one of the bytes will be lost.) The serial port receive

and transmit registers are both accessed at Special Function Reg-

ister SBUF. Writing to SBUF loads the transmit register, and

reading SBUF accesses a physically separate receive register.

The serial port can operate in 4 modes:

Mode 0:

Serial data enters and exits through RxD. TxD outputs

the shift clock. 8 bits are transmitted/received (LSB first). The

baud rate is fixed at 1/6 the CPU clock frequency.

Mode 1:

10 bits are transmitted (through TxD) or received

(through RxD) : a start bit ( 0 ), 8 data bits (LSB first), and a stop

bit (1). On receive, the stop bit goes into RB8 in Special Function

Mode 2:

11 bits are transmitted (through TxD) or received

(through RxD) : start bit (0), 8 data bits (LSB first), a program-

mable 9th data bit, and a stop bit (1). On Transmit, the 9th data

bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for

example, the parity bit (P, in the PSW) could be moved into TB8.

On receive, the 9th data bit goes into RB8 in Special Function

programmable to either 1/16 or 1/32 the CPU clock frequency.

Mode 3:

11 bits are transmitted (through TxD) or received

(through RxD) : a start bit (0), 8 data bits (LSB first), a program-

mable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same

as Mode 2 in all respects except baud rate. The baud rate in Mode

3 is variable.

In all four modes, transmission is initiated by any instruction that

uses SBUF as a destination register. Reception is initiated in

Mode 0 by the condition RI = 0 and REN = 1. Reception is initi-

ated in the other modes by the incoming start bit if REN = 1.

Multiprocessor Communications

Modes 2 and 3 have a special provision for multiprocessor com-

munications. In these modes, 9 data bits are received. The 9th one

goes into RB8. Then comes a stop bit. The port can be pro-

grammed such that when the stop bit is received, the serial port

interrupt will be activated only if RB8 = 1. This feature is enabled

by setting bit SM2 in SCON. A way to use this feature in multi-

processor systems is as follows:

When the master processor wants to transmit a block of data to

one of several slaves, it first sends out an address byte which

identifies the target slave. An address byte differs from a data

byte in that the 9th bit is 1 in an address byte and 0 in a data byte.

With SM2 = 1, no slave will be interrupted by a data byte. An ad-

dress byte, however, will interrupt all slaves, so that each slave

can examine the received byte and see if it is being addressed.

The addressed slave will clear its SM2 bit and prepare to receive

the data bytes that will be coming. The slaves that weren't being

addressed leave their SM2s set and go on about their business, ig-

noring the coming data bytes.

SM2 has no effect in Mode 0, and in Mode 1 can be used to check

the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the

receive interrupt will not be activated unless a valid stop bit is re-

ceived.

Serial Port Control Register

The serial port control and status register is the Special Function

only the mode selection bits, but also the 9th data bit for transmit

and receive (TB8 and RB8), and the serial port interrupt bits (TI

and RI).

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