HMS91C8032 datasheet(41/157 Pages) HYNIX

41 / 157 page

HMS91C8032/97C8032

NOV., 2001 Ver 1.02

ADCCON: ADC CONTROL REGISTER. BIT ADDRESSABLE. : 84H

ADCCON.7

Reserved for future use *

ADCEN

ADCCON.6

ADC Enable flag. This bit is a write-only register.

ADCCON.5

Reserved for future use *

ADCCH2

ADCCON.4

See Table 4-23. This bit is a write-only register.

ADCCH1

ADCCON.3

See Table 4-23. This bit is a write-only register.

ADCCH0

ADCCON.2

See Table 4-23. This bit is a write-only register.

ADCST

ADCCON.1

Software START control for ADC. A logic 1 starts A/D conversion. This bit is a write-only register.

ADCSF

ADCCON.0

A/D conversion completion flag. Set by hardware when ADC operation complete. Cleared by hardware

when this flag is read.

SFRPG: SFR PAGE REGISTER. NOT BIT ADDRESSABLE. : FFH

SFRPG.7

Reserved for future use *

SFRPG.6

Reserved for future use *

SFRPG.5

Reserved for future use *

SFRPG.4

Reserved for future use *

SFRPG.3

Reserved for future use *

SFRPG.2

Reserved for future use *

SFRPG.1

Reserved for future use *

SFRP

SFRPG.0

Software SFR page0/page1 control flag. A logic 1 switches to SFR page 1.

SCMOD2

SCMOD1

SCMOD0

Select system clock

fxx

fxx / 2

fxx / 4

fxx / 8

fxx / 16

Table 4-22 Select System Clock

ADCEN

ADCCH2

ADCCH1

ADCCH0

ADCST

ADCSF

ADCCH2

ADCCH1

ADCCH0

Select ADC channel

Select channel 0

Select channel 1

Select channel 2

Select channel 3

Select channel 4

Select channel 5

Select channel 6

Select channel 7

Table 4-23 ADC Channel Select

-------

SFRP

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