70353C datasheet(64/76 Pages) MICROCHIP

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dsPIC33E/PIC24E Family Reference Manual

DS70353C-page 21-64

A node starts out in the Error Active mode. When any one of the two Error Counters equals or

exceeds a value of 127, the node enters a state known as Error Passive. When the Transmit

Error Counter exceeds a value of 255, the node enters the Bus OFF state.

• An Error Active node transmits an Active Error Frame when it detects errors

• An Error Passive node transmits a Passive Error Frame when it detects errors

• A node that is in the Bus OFF state transmits nothing on the bus

In addition, the ECAN module employs an error warning feature that warns the user application

(when the Transmit Error Counter equals or exceeds 96) before the node enters the Error

Passive state, as illustrated in Figure 21-18.

Figure 21-18: Error Modes

21.10.2.1 TRANSMITTER IN ERROR PASSIVE STATE

The Transmitter Error Passive (TXBP) bit (CiINTF<12>) is set when the Transmit Error Counter

equals or exceeds 128 and generates an error interrupt (CiINTF<5>) upon entry into the Error

Passive state. The Transmit Error Passive flag is cleared automatically by the hardware, if the

Transmit Error Counter becomes less than 128 or greater than 255.

21.10.2.2 RECEIVER IN ERROR PASSIVE STATE

The Receiver Error Passive (RXBP) bit (CiINTF<11>) is set when the Receive Error Counter

equals or exceeds 128 and generates an error interrupt (CiINTF<5>) upon entry into the Error

Passive state. The Receive Error Passive flag is cleared automatically by the hardware, if the

Receive Error Counter becomes less than 128 or greater than 255.

21.10.2.3 TRANSMITTER IN BUS OFF STATE

The Transmitter Bus OFF (TXBO) bit (CiINTF<13>) is set when the Transmit Error Counter

equals or exceeds 256 and generates an error interrupt (CiINTF<5>)

21.10.2.4 TRANSMITTER IN ERROR WARNING STATE

The Transmitter Error Warn (TXWAR) bit (CiINTF<10>) is set when the Transmit Error Counter

is in the range of 96 and 127 (inclusive), and generates an error interrupt (CiINTF<5>) upon entry

into the Error Warn state. The Transmit Error Warn flag is cleared automatically by the hardware,

if the Transmit Error Counter becomes less than 96 or greater than 127.

21.10.2.5 RECEIVER IN ERROR WARNING STATE

The Receiver Error Warn (RXWAR) bit (CiINTF<9>) is set when the Receive Error Counter is in

the range of 96 and 127 (inclusive) and generates an error interrupt (CiINTF<5>) upon entry into

the Error Warn state. The Receive Error Warn flag is cleared automatically by the hardware if the

Receive Error Counter becomes less than 96.

Additionally, there is an Error State Warning Flag (EWARN) bit (CiINTF<8>), which is set if at

least one of the error counters equals or exceeds the error warning limit of 96. EWARN is reset

if both error counters are less than the error warning limit.

Bus

OFF

Error

Active

Error

Passive

RERRCNT > 127 or

TERRCNT > 127

RERRCNT < 127 and

TERRCNT < 127

TERRCNT > 255

128 occurrences of

11 consecutive

“recessive” bits

Reset

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