70353C datasheet(67/76 Pages) MICROCHIP

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DS70353C-page 21-67

Section 21. Enhanced Controller Area Network (ECAN™)

21.11.3.2 RECEIVE BUFFER INTERRUPT

When a message is successfully received and loaded into one of the receive buffers (message

buffers 0 to 31), the receive buffer interrupt (CiINTF<1>) is activated after the module sets the

RXFULn bits in the CiRXFULm registers. The ICODE<6:0> bits (CiVEC<6:0>) will indicate the

particular buffer that generated the interrupt. The receive buffer interrupt must be cleared in the

ISR by clearing the RBIF bit.

21.11.3.3 RECEIVE BUFFER OVERFLOW INTERRUPT

When a message is successfully received but the designated buffer is full, the receive overflow

interrupt (CiINTF<2>) is activated after the module sets the RXOVFn bits in the CiRXOVFm

registers. The ICODE<6:0> bits (CiVEC<6:0>) indicate which buffer generated the interrupt. The

receive buffer overflow interrupt must be cleared in the ISR by clearing the RBOVIF bit

(CiINTF<2>).

21.11.3.4 FIFO ALMOST FULL INTERRUPT

When the FIFO has only one remaining available buffer, the FIFO interrupt (CiINTF<3>) is

activated after the module sets the RXFULn bits in the CiRXFULm registers for the next to last

available buffer. The ICODE<6:0> bits (CiVEC<6:0>) indicate the FIFO overflow condition. The

FIFO almost full interrupt must be cleared in the ISR by clearing the FIFOIF bit (CiINTF<3>).

21.11.3.5 ERROR INTERRUPT

The error interrupt (CiINTF<5>) is generated by five sources:

• TX Error Warn

• RX Error Warn

• TX Error Passive

• RX Error Passive

• TX Bus Off

The ICODE<6:0> bits (CiVEC<6:0>) indicate the Error condition. The error interrupt must be

cleared in the ISR by clearing the ERRIF bit (CiINTF<5>).

21.11.3.6 WAKE-UP INTERRUPT

In Sleep mode, the device monitors the ECAN receive pin (CiRX) for bus activity. A wake-up

(CiINTF<6>) interrupt is generated when bus activity is detected. The ICODE<6:0> bits

(CiVEC<6:0>) indicate the wake-up condition. The wake-up interrupt must be cleared in the ISR

by clearing the WAKIF bit (CiINTF<6>).

21.11.3.7 INVALID MESSAGE INTERRUPT

The invalid message/transmission interrupt is generated for any other type of errors during

message reception or transmission.

70353C Datasheet(PDF) 67 Page - Microchip Technology