AN3286 datasheet(6/42 Pages) STMICROELECTRONICS

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Adapter features

AN3286

6/42

Doc ID 17998 Rev 1

Adapter features

Table 1 lists the electrical specifications of the demonstration board.

1.1

Circuit description

The power supply is set in a flyback topology and its schematic is shown in Figure 2. The

input section includes protection elements (fuse and NTC for inrush current limiting), a filter

for EMC suppression (C1, T2, C13), a diode bridge (BR1), and an electrolytic bulk capacitor

(C3) as the front-end AC-DC converter. The transformer uses a standard E25 ferrite core.

A Transil™ clamp network is used for leakage inductance demagnetization.

At power-up the DRAIN pin supplies the internal HV startup current generator which

charges the C4 capacitor up to VDDon. At this point the power MOSFET starts switching, the

generator is turned off, and the IC is powered by the energy stored in C4, until the auxiliary

winding voltage becomes high enough to sustain the operation through D1 and R1. The

value of the resistor R3 between the ZCD and GND pins defines the VIPer25 current limit

and, in conjunction with D2 and R14, also realizes the overvoltage protection function.

The ZCD pin is also responsible for the quasi-resonant operation, being a transformer

demagnetization sensing input triggering the MOSFET turn-on.

Converter power capability variations with the mains voltage, inherent in quasi-resonant

operation, are compensated by the R3-R15 voltage divider, which implements the line

voltage feed-forward correction function. At very light or disconnected load the device enters

burst mode, allowing to keep low the consumption from the mains in such conditions

(< 50 mW at 265 VAC). The output rectifier D4 has been selected according to the calculated

maximum reverse voltage, forward voltage drop, and power dissipation, and is a power

Schottky type. The output voltage regulation is performed by secondary feedback with

a TS431 driving an optocoupler, in this case, a PC817, ensuring the required insulation

between primary and secondary. The optotransistor drives directly the FB pin of the

VIPer25, which is connected to the compensation network made up of C6, C7, and R12.

A small LC network has been added at the output in order to filter the high frequency ripple

without increasing the output capacitor size and a 100 nF capacitor has been placed very

close to the output connector solder points, to limit the spike amplitude. Through jumper J,

the BR pin can be either connected to a voltage divider sensing the mains rectified voltage

in order to realize a brownout protection, or to GND. In the latter case, the RH1-RH2-RL

branch can be disconnected from the mains in order to reach minimum standby

consumption.

Table 1.

Electrical specifications

Parameter

Symbol

Value

Input voltage range

VIN_AC

[90 VAC - 265 VAC]

Output voltage

VOUT

5 V

Max. output current

IOUTmax

2 A

Precision of output regulation

ΔVOUT_LF

±5%

High frequency output voltage ripple

ΔVOUT_HF

50 mV

Max. ambient operating temperature

60 °C

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