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First-in first-out (FIFO) buffer

AN4506

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First-in first-out (FIFO) buffer

In order to limit intervention from the host processor and facilitate post-processing data for

event recognition, the L3GD20H embeds a first-in first-out buffer (FIFO) for each of the

three output channels, X, Y, and Z.

FIFO use allows consistent power saving for the system; it can wake up only when needed

and burst the significant data out from the FIFO.

The FIFO buffer can work according to seven different modes that guarantee a high-level of

flexibility during application development: Bypass mode, FIFO mode, Stream mode,

Dynamic Stream mode, Stream-to-FIFO mode, Bypass-to-Stream mode and Bypass-to-

FIFO mode.

The programmable FIFO threshold and FIFO overrun event can be enabled to generate

dedicated interrupts on the DRDY/INT2 pin.

6.1

FIFO description

The FIFO buffer is able to store up to 32 angular rate samples of 16 bits for each channel;

data are stored in the 16-bit 2’s complement left-justified representation.

The data samples set consists of 6 bytes (Xl, Xh, Yl, Yh, Zl, and Zh) and they are released

to the FIFO at the selected output data rate (ODR).

The new sample set is placed in the first empty FIFO slot until the buffer is full, therefore, the

oldest value is overwritten.

Table 27. FIFO buffer full representation (32nd sample set stored)

Output

registers

0x28h

0x29h

0x2Ah

0x2Bh

0x2Ch

0x2Dh

Xl(0)

Xh(0)

Yl(0)

Yh(0)

Zl(0)

Zh(0)

FIFO index

FIFO sample set

FIFO(0)

Xl(0)

Xh(0)

Yl(0)

Yh(0)

Zl(0)

Zh(0)

FIFO(1)

Xl(1)

Xh(1)

Yl(1)

Yh(1)

Zl(1)

Zh(1)

FIFO(2)

Xl(2)

Xh(2)

Yl(2)

Yh(2)

Zl(2)

Zh(2)

FIFO(3)

Xl(3)

Xh(3)

Yl(3)

Yh(3)

Zl(3)

Zh(3)

...

FIFO(30)

Xl(30)

Xh(30)

Yl(30)

Yh(30)

Zl(30)

Zh(30)

FIFO(31)

Xl(31)

Xh(31)

Yl(31)

Yh(31)

Zl(31)

Zh(31)

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